208 lines
10 KiB
YAML
208 lines
10 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
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# Make sure we do not treat an argument as having zero false lanes
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-arm-none-eabihf"
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define zeroext i8 @test7(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, ptr nocapture noundef readnone %c, i32 noundef %n, <16 x i8> noundef %vx) {
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entry:
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%cmp10 = icmp sgt i32 %n, 0
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br i1 %cmp10, label %while.body.preheader, label %while.end
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while.body.preheader: ; preds = %entry
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%0 = add i32 %n, 15
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%umin = call i32 @llvm.umin.i32(i32 %n, i32 16)
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%1 = sub i32 %0, %umin
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%2 = lshr i32 %1, 4
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%3 = add nuw nsw i32 %2, 1
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%4 = call i32 @llvm.start.loop.iterations.i32(i32 %3)
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br label %while.body
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while.body: ; preds = %while.body.preheader, %while.body
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%a.addr.014 = phi ptr [ %add.ptr, %while.body ], [ %a, %while.body.preheader ]
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%b.addr.013 = phi ptr [ %add.ptr2, %while.body ], [ %b, %while.body.preheader ]
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%n.addr.012 = phi i32 [ %12, %while.body ], [ %n, %while.body.preheader ]
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%sum.011 = phi i8 [ %conv1, %while.body ], [ 0, %while.body.preheader ]
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%5 = phi i32 [ %4, %while.body.preheader ], [ %13, %while.body ]
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%6 = tail call <16 x i1> @llvm.arm.mve.vctp8(i32 %n.addr.012)
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%7 = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %a.addr.014, i32 1, <16 x i1> %6, <16 x i8> zeroinitializer)
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%8 = tail call <16 x i8> @llvm.masked.load.v16i8.p0(ptr %b.addr.013, i32 1, <16 x i1> %6, <16 x i8> zeroinitializer)
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%9 = tail call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %7, <16 x i8> %8, <16 x i1> %6, <16 x i8> %vx)
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%10 = tail call i32 @llvm.arm.mve.addv.v16i8(<16 x i8> %9, i32 1)
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%11 = trunc i32 %10 to i8
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%conv1 = add i8 %sum.011, %11
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%add.ptr = getelementptr inbounds i8, ptr %a.addr.014, i32 16
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%add.ptr2 = getelementptr inbounds i8, ptr %b.addr.013, i32 16
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%12 = add i32 %n.addr.012, -16
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%13 = call i32 @llvm.loop.decrement.reg.i32(i32 %5, i32 1)
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%14 = icmp ne i32 %13, 0
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br i1 %14, label %while.body, label %while.end
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while.end: ; preds = %while.body, %entry
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%sum.0.lcssa = phi i8 [ 0, %entry ], [ %conv1, %while.body ]
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ret i8 %sum.0.lcssa
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}
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declare <16 x i1> @llvm.arm.mve.vctp8(i32)
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declare <16 x i8> @llvm.masked.load.v16i8.p0(ptr nocapture, i32 immarg, <16 x i1>, <16 x i8>)
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declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>)
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declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32)
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declare i32 @llvm.umin.i32(i32, i32)
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declare i32 @llvm.start.loop.iterations.i32(i32)
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declare i32 @llvm.loop.decrement.reg.i32(i32, i32)
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...
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---
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name: test7
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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callsEHReturn: false
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callsUnwindInit: false
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hasEHCatchret: false
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hasEHScopes: false
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hasEHFunclets: false
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failsVerification: false
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tracksDebugUserValues: true
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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- { reg: '$q0', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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functionContext: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: test7
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.1(0x50000000), %bb.3(0x30000000)
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; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r3, $r7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK-NEXT: dead $r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_register $r7
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; CHECK-NEXT: tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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; CHECK-NEXT: renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: tBcc %bb.3, 11 /* CC::lt */, killed $cpsr
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.while.body.preheader:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: liveins: $q0, $r0, $r1, $r3, $r12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $r2 = t2SUBri renamable $r3, 16, 14 /* CC::al */, $noreg, def $cpsr
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; CHECK-NEXT: renamable $r2 = t2CSEL killed renamable $r2, renamable $r12, 2, implicit killed $cpsr
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; CHECK-NEXT: renamable $lr = t2ADDri killed renamable $r2, 15, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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; CHECK-NEXT: renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 35, 14 /* CC::al */, $noreg, $noreg
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; CHECK-NEXT: $lr = t2DLS killed renamable $r2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.while.body (align 4):
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; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK-NEXT: liveins: $lr, $q0, $r0, $r1, $r3, $r12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg
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; CHECK-NEXT: MVE_VPST 4, implicit $vpr
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; CHECK-NEXT: renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.a.addr.014, align 1)
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; CHECK-NEXT: renamable $r1, renamable $q2 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.b.addr.013, align 1)
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; CHECK-NEXT: $q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
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; CHECK-NEXT: MVE_VPST 8, implicit $vpr
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; CHECK-NEXT: renamable $q3 = MVE_VADDi8 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, renamable $lr, killed renamable $q3
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; CHECK-NEXT: renamable $r12 = MVE_VADDVu8acc killed renamable $r12, killed renamable $q3, 0, $noreg, renamable $lr
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; CHECK-NEXT: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
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; CHECK-NEXT: $lr = t2LEUpdate killed renamable $lr, %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.while.end:
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; CHECK-NEXT: liveins: $r12
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $r0 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg
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; CHECK-NEXT: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
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bb.0.entry:
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successors: %bb.1(0x50000000), %bb.3(0x30000000)
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liveins: $q0, $r0, $r1, $r3, $r7, $lr
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frame-setup tPUSH 14 /* CC::al */, $noreg, $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$r7 = frame-setup tMOVr $sp, 14 /* CC::al */, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_register $r7
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tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
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renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
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tBcc %bb.3, 11 /* CC::lt */, killed $cpsr
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bb.1.while.body.preheader:
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successors: %bb.2(0x80000000)
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liveins: $q0, $r0, $r1, $r3, $r12
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renamable $r2 = t2SUBri renamable $r3, 16, 14 /* CC::al */, $noreg, def $cpsr
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renamable $r2 = t2CSEL killed renamable $r2, renamable $r12, 2, implicit killed $cpsr
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renamable $lr = t2ADDri killed renamable $r2, 15, 14 /* CC::al */, $noreg, $noreg
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renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $lr, 35, 14 /* CC::al */, $noreg, $noreg
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renamable $lr = t2DoLoopStartTP killed renamable $r2, renamable $r3
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bb.2.while.body (align 4):
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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liveins: $lr, $q0, $r0, $r1, $r3, $r12
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renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg
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MVE_VPST 4, implicit $vpr
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renamable $r0, renamable $q1 = MVE_VLDRBU8_post killed renamable $r0, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.a.addr.014, align 1)
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renamable $r1, renamable $q2 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.b.addr.013, align 1)
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$q3 = MQPRCopy $q0
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MVE_VPST 8, implicit $vpr
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renamable $q3 = MVE_VADDi8 killed renamable $q1, killed renamable $q2, 1, killed renamable $vpr, renamable $lr, killed renamable $q3
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renamable $r12 = MVE_VADDVu8acc killed renamable $r12, killed renamable $q3, 0, $noreg, renamable $lr
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renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14 /* CC::al */, $noreg
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renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.3, 14 /* CC::al */, $noreg
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bb.3.while.end:
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liveins: $r12
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renamable $r0 = t2UXTB killed renamable $r12, 0, 14 /* CC::al */, $noreg
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frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
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...
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