555 lines
21 KiB
C++
555 lines
21 KiB
C++
//===- RISCV.cpp ----------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "ABIInfoImpl.h"
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#include "TargetInfo.h"
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using namespace clang;
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using namespace clang::CodeGen;
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//===----------------------------------------------------------------------===//
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// RISC-V ABI Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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class RISCVABIInfo : public DefaultABIInfo {
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private:
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// Size of the integer ('x') registers in bits.
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unsigned XLen;
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// Size of the floating point ('f') registers in bits. Note that the target
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// ISA might have a wider FLen than the selected ABI (e.g. an RV32IF target
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// with soft float ABI has FLen==0).
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unsigned FLen;
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const int NumArgGPRs;
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const int NumArgFPRs;
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const bool EABI;
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bool detectFPCCEligibleStructHelper(QualType Ty, CharUnits CurOff,
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llvm::Type *&Field1Ty,
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CharUnits &Field1Off,
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llvm::Type *&Field2Ty,
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CharUnits &Field2Off) const;
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public:
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RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, unsigned FLen,
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bool EABI)
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: DefaultABIInfo(CGT), XLen(XLen), FLen(FLen), NumArgGPRs(EABI ? 6 : 8),
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NumArgFPRs(FLen != 0 ? 8 : 0), EABI(EABI) {}
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// DefaultABIInfo's classifyReturnType and classifyArgumentType are
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// non-virtual, but computeInfo is virtual, so we overload it.
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void computeInfo(CGFunctionInfo &FI) const override;
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ABIArgInfo classifyArgumentType(QualType Ty, bool IsFixed, int &ArgGPRsLeft,
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int &ArgFPRsLeft) const;
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ABIArgInfo classifyReturnType(QualType RetTy) const;
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Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
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QualType Ty) const override;
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ABIArgInfo extendType(QualType Ty) const;
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bool detectFPCCEligibleStruct(QualType Ty, llvm::Type *&Field1Ty,
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CharUnits &Field1Off, llvm::Type *&Field2Ty,
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CharUnits &Field2Off, int &NeededArgGPRs,
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int &NeededArgFPRs) const;
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ABIArgInfo coerceAndExpandFPCCEligibleStruct(llvm::Type *Field1Ty,
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CharUnits Field1Off,
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llvm::Type *Field2Ty,
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CharUnits Field2Off) const;
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ABIArgInfo coerceVLSVector(QualType Ty) const;
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};
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} // end anonymous namespace
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void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
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QualType RetTy = FI.getReturnType();
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if (!getCXXABI().classifyReturnType(FI))
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FI.getReturnInfo() = classifyReturnType(RetTy);
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// IsRetIndirect is true if classifyArgumentType indicated the value should
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// be passed indirect, or if the type size is a scalar greater than 2*XLen
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// and not a complex type with elements <= FLen. e.g. fp128 is passed direct
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// in LLVM IR, relying on the backend lowering code to rewrite the argument
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// list and pass indirectly on RV32.
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bool IsRetIndirect = FI.getReturnInfo().getKind() == ABIArgInfo::Indirect;
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if (!IsRetIndirect && RetTy->isScalarType() &&
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getContext().getTypeSize(RetTy) > (2 * XLen)) {
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if (RetTy->isComplexType() && FLen) {
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QualType EltTy = RetTy->castAs<ComplexType>()->getElementType();
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IsRetIndirect = getContext().getTypeSize(EltTy) > FLen;
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} else {
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// This is a normal scalar > 2*XLen, such as fp128 on RV32.
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IsRetIndirect = true;
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}
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}
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int ArgGPRsLeft = IsRetIndirect ? NumArgGPRs - 1 : NumArgGPRs;
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int ArgFPRsLeft = NumArgFPRs;
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int NumFixedArgs = FI.getNumRequiredArgs();
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int ArgNum = 0;
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for (auto &ArgInfo : FI.arguments()) {
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bool IsFixed = ArgNum < NumFixedArgs;
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ArgInfo.info =
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classifyArgumentType(ArgInfo.type, IsFixed, ArgGPRsLeft, ArgFPRsLeft);
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ArgNum++;
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}
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}
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// Returns true if the struct is a potential candidate for the floating point
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// calling convention. If this function returns true, the caller is
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// responsible for checking that if there is only a single field then that
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// field is a float.
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bool RISCVABIInfo::detectFPCCEligibleStructHelper(QualType Ty, CharUnits CurOff,
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llvm::Type *&Field1Ty,
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CharUnits &Field1Off,
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llvm::Type *&Field2Ty,
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CharUnits &Field2Off) const {
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bool IsInt = Ty->isIntegralOrEnumerationType();
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bool IsFloat = Ty->isRealFloatingType();
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if (IsInt || IsFloat) {
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uint64_t Size = getContext().getTypeSize(Ty);
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if (IsInt && Size > XLen)
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return false;
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// Can't be eligible if larger than the FP registers. Handling of half
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// precision values has been specified in the ABI, so don't block those.
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if (IsFloat && Size > FLen)
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return false;
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// Can't be eligible if an integer type was already found (int+int pairs
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// are not eligible).
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if (IsInt && Field1Ty && Field1Ty->isIntegerTy())
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return false;
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if (!Field1Ty) {
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Field1Ty = CGT.ConvertType(Ty);
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Field1Off = CurOff;
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return true;
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}
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if (!Field2Ty) {
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Field2Ty = CGT.ConvertType(Ty);
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Field2Off = CurOff;
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return true;
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}
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return false;
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}
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if (auto CTy = Ty->getAs<ComplexType>()) {
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if (Field1Ty)
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return false;
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QualType EltTy = CTy->getElementType();
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if (getContext().getTypeSize(EltTy) > FLen)
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return false;
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Field1Ty = CGT.ConvertType(EltTy);
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Field1Off = CurOff;
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Field2Ty = Field1Ty;
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Field2Off = Field1Off + getContext().getTypeSizeInChars(EltTy);
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return true;
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}
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if (const ConstantArrayType *ATy = getContext().getAsConstantArrayType(Ty)) {
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uint64_t ArraySize = ATy->getSize().getZExtValue();
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QualType EltTy = ATy->getElementType();
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// Non-zero-length arrays of empty records make the struct ineligible for
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// the FP calling convention in C++.
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if (const auto *RTy = EltTy->getAs<RecordType>()) {
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if (ArraySize != 0 && isa<CXXRecordDecl>(RTy->getDecl()) &&
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isEmptyRecord(getContext(), EltTy, true, true))
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return false;
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}
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CharUnits EltSize = getContext().getTypeSizeInChars(EltTy);
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for (uint64_t i = 0; i < ArraySize; ++i) {
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bool Ret = detectFPCCEligibleStructHelper(EltTy, CurOff, Field1Ty,
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Field1Off, Field2Ty, Field2Off);
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if (!Ret)
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return false;
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CurOff += EltSize;
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}
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return true;
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}
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if (const auto *RTy = Ty->getAs<RecordType>()) {
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// Structures with either a non-trivial destructor or a non-trivial
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// copy constructor are not eligible for the FP calling convention.
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if (getRecordArgABI(Ty, CGT.getCXXABI()))
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return false;
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if (isEmptyRecord(getContext(), Ty, true, true))
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return true;
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const RecordDecl *RD = RTy->getDecl();
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// Unions aren't eligible unless they're empty (which is caught above).
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if (RD->isUnion())
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return false;
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const ASTRecordLayout &Layout = getContext().getASTRecordLayout(RD);
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// If this is a C++ record, check the bases first.
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if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) {
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for (const CXXBaseSpecifier &B : CXXRD->bases()) {
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const auto *BDecl =
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cast<CXXRecordDecl>(B.getType()->castAs<RecordType>()->getDecl());
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CharUnits BaseOff = Layout.getBaseClassOffset(BDecl);
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bool Ret = detectFPCCEligibleStructHelper(B.getType(), CurOff + BaseOff,
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Field1Ty, Field1Off, Field2Ty,
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Field2Off);
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if (!Ret)
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return false;
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}
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}
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int ZeroWidthBitFieldCount = 0;
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for (const FieldDecl *FD : RD->fields()) {
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uint64_t FieldOffInBits = Layout.getFieldOffset(FD->getFieldIndex());
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QualType QTy = FD->getType();
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if (FD->isBitField()) {
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unsigned BitWidth = FD->getBitWidthValue(getContext());
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// Allow a bitfield with a type greater than XLen as long as the
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// bitwidth is XLen or less.
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if (getContext().getTypeSize(QTy) > XLen && BitWidth <= XLen)
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QTy = getContext().getIntTypeForBitwidth(XLen, false);
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if (BitWidth == 0) {
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ZeroWidthBitFieldCount++;
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continue;
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}
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}
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bool Ret = detectFPCCEligibleStructHelper(
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QTy, CurOff + getContext().toCharUnitsFromBits(FieldOffInBits),
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Field1Ty, Field1Off, Field2Ty, Field2Off);
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if (!Ret)
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return false;
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// As a quirk of the ABI, zero-width bitfields aren't ignored for fp+fp
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// or int+fp structs, but are ignored for a struct with an fp field and
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// any number of zero-width bitfields.
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if (Field2Ty && ZeroWidthBitFieldCount > 0)
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return false;
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}
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return Field1Ty != nullptr;
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}
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return false;
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}
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// Determine if a struct is eligible for passing according to the floating
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// point calling convention (i.e., when flattened it contains a single fp
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// value, fp+fp, or int+fp of appropriate size). If so, NeededArgFPRs and
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// NeededArgGPRs are incremented appropriately.
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bool RISCVABIInfo::detectFPCCEligibleStruct(QualType Ty, llvm::Type *&Field1Ty,
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CharUnits &Field1Off,
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llvm::Type *&Field2Ty,
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CharUnits &Field2Off,
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int &NeededArgGPRs,
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int &NeededArgFPRs) const {
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Field1Ty = nullptr;
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Field2Ty = nullptr;
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NeededArgGPRs = 0;
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NeededArgFPRs = 0;
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bool IsCandidate = detectFPCCEligibleStructHelper(
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Ty, CharUnits::Zero(), Field1Ty, Field1Off, Field2Ty, Field2Off);
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if (!Field1Ty)
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return false;
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// Not really a candidate if we have a single int but no float.
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if (Field1Ty && !Field2Ty && !Field1Ty->isFloatingPointTy())
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return false;
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if (!IsCandidate)
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return false;
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if (Field1Ty && Field1Ty->isFloatingPointTy())
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NeededArgFPRs++;
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else if (Field1Ty)
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NeededArgGPRs++;
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if (Field2Ty && Field2Ty->isFloatingPointTy())
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NeededArgFPRs++;
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else if (Field2Ty)
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NeededArgGPRs++;
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return true;
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}
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// Call getCoerceAndExpand for the two-element flattened struct described by
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// Field1Ty, Field1Off, Field2Ty, Field2Off. This method will create an
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// appropriate coerceToType and unpaddedCoerceToType.
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ABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct(
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llvm::Type *Field1Ty, CharUnits Field1Off, llvm::Type *Field2Ty,
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CharUnits Field2Off) const {
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SmallVector<llvm::Type *, 3> CoerceElts;
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SmallVector<llvm::Type *, 2> UnpaddedCoerceElts;
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if (!Field1Off.isZero())
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CoerceElts.push_back(llvm::ArrayType::get(
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llvm::Type::getInt8Ty(getVMContext()), Field1Off.getQuantity()));
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CoerceElts.push_back(Field1Ty);
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UnpaddedCoerceElts.push_back(Field1Ty);
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if (!Field2Ty) {
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return ABIArgInfo::getCoerceAndExpand(
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llvm::StructType::get(getVMContext(), CoerceElts, !Field1Off.isZero()),
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UnpaddedCoerceElts[0]);
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}
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CharUnits Field2Align =
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CharUnits::fromQuantity(getDataLayout().getABITypeAlign(Field2Ty));
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CharUnits Field1End = Field1Off +
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CharUnits::fromQuantity(getDataLayout().getTypeStoreSize(Field1Ty));
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CharUnits Field2OffNoPadNoPack = Field1End.alignTo(Field2Align);
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CharUnits Padding = CharUnits::Zero();
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if (Field2Off > Field2OffNoPadNoPack)
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Padding = Field2Off - Field2OffNoPadNoPack;
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else if (Field2Off != Field2Align && Field2Off > Field1End)
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Padding = Field2Off - Field1End;
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bool IsPacked = !Field2Off.isMultipleOf(Field2Align);
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if (!Padding.isZero())
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CoerceElts.push_back(llvm::ArrayType::get(
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llvm::Type::getInt8Ty(getVMContext()), Padding.getQuantity()));
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CoerceElts.push_back(Field2Ty);
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UnpaddedCoerceElts.push_back(Field2Ty);
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auto CoerceToType =
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llvm::StructType::get(getVMContext(), CoerceElts, IsPacked);
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auto UnpaddedCoerceToType =
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llvm::StructType::get(getVMContext(), UnpaddedCoerceElts, IsPacked);
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return ABIArgInfo::getCoerceAndExpand(CoerceToType, UnpaddedCoerceToType);
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}
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// Fixed-length RVV vectors are represented as scalable vectors in function
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// args/return and must be coerced from fixed vectors.
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ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty) const {
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assert(Ty->isVectorType() && "expected vector type!");
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const auto *VT = Ty->castAs<VectorType>();
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assert(VT->getElementType()->isBuiltinType() && "expected builtin type!");
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auto VScale =
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getContext().getTargetInfo().getVScaleRange(getContext().getLangOpts());
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unsigned NumElts = VT->getNumElements();
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llvm::Type *EltType;
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if (VT->getVectorKind() == VectorKind::RVVFixedLengthMask) {
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NumElts *= 8;
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EltType = llvm::Type::getInt1Ty(getVMContext());
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} else {
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assert(VT->getVectorKind() == VectorKind::RVVFixedLengthData &&
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"Unexpected vector kind");
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EltType = CGT.ConvertType(VT->getElementType());
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}
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// The MinNumElts is simplified from equation:
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// NumElts / VScale =
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// (EltSize * NumElts / (VScale * RVVBitsPerBlock))
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// * (RVVBitsPerBlock / EltSize)
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llvm::ScalableVectorType *ResType =
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llvm::ScalableVectorType::get(EltType, NumElts / VScale->first);
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return ABIArgInfo::getDirect(ResType);
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}
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ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
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int &ArgGPRsLeft,
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int &ArgFPRsLeft) const {
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assert(ArgGPRsLeft <= NumArgGPRs && "Arg GPR tracking underflow");
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Ty = useFirstFieldIfTransparentUnion(Ty);
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// Structures with either a non-trivial destructor or a non-trivial
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// copy constructor are always passed indirectly.
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if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
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if (ArgGPRsLeft)
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ArgGPRsLeft -= 1;
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return getNaturalAlignIndirect(Ty, /*ByVal=*/RAA ==
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CGCXXABI::RAA_DirectInMemory);
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}
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// Ignore empty structs/unions.
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if (isEmptyRecord(getContext(), Ty, true))
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return ABIArgInfo::getIgnore();
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uint64_t Size = getContext().getTypeSize(Ty);
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// Pass floating point values via FPRs if possible.
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if (IsFixed && Ty->isFloatingType() && !Ty->isComplexType() &&
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FLen >= Size && ArgFPRsLeft) {
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ArgFPRsLeft--;
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return ABIArgInfo::getDirect();
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}
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// Complex types for the hard float ABI must be passed direct rather than
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// using CoerceAndExpand.
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if (IsFixed && Ty->isComplexType() && FLen && ArgFPRsLeft >= 2) {
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QualType EltTy = Ty->castAs<ComplexType>()->getElementType();
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if (getContext().getTypeSize(EltTy) <= FLen) {
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ArgFPRsLeft -= 2;
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return ABIArgInfo::getDirect();
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}
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}
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if (IsFixed && FLen && Ty->isStructureOrClassType()) {
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llvm::Type *Field1Ty = nullptr;
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llvm::Type *Field2Ty = nullptr;
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CharUnits Field1Off = CharUnits::Zero();
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CharUnits Field2Off = CharUnits::Zero();
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int NeededArgGPRs = 0;
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int NeededArgFPRs = 0;
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bool IsCandidate =
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detectFPCCEligibleStruct(Ty, Field1Ty, Field1Off, Field2Ty, Field2Off,
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NeededArgGPRs, NeededArgFPRs);
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if (IsCandidate && NeededArgGPRs <= ArgGPRsLeft &&
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NeededArgFPRs <= ArgFPRsLeft) {
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ArgGPRsLeft -= NeededArgGPRs;
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ArgFPRsLeft -= NeededArgFPRs;
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return coerceAndExpandFPCCEligibleStruct(Field1Ty, Field1Off, Field2Ty,
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Field2Off);
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}
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}
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uint64_t NeededAlign = getContext().getTypeAlign(Ty);
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// Determine the number of GPRs needed to pass the current argument
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// according to the ABI. 2*XLen-aligned varargs are passed in "aligned"
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// register pairs, so may consume 3 registers.
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// TODO: To be compatible with GCC's behaviors, we don't align registers
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// currently if we are using ILP32E calling convention. This behavior may be
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// changed when RV32E/ILP32E is ratified.
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int NeededArgGPRs = 1;
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if (!IsFixed && NeededAlign == 2 * XLen)
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NeededArgGPRs = 2 + (EABI && XLen == 32 ? 0 : (ArgGPRsLeft % 2));
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else if (Size > XLen && Size <= 2 * XLen)
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NeededArgGPRs = 2;
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if (NeededArgGPRs > ArgGPRsLeft) {
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NeededArgGPRs = ArgGPRsLeft;
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}
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ArgGPRsLeft -= NeededArgGPRs;
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if (!isAggregateTypeForABI(Ty) && !Ty->isVectorType()) {
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// Treat an enum type as its underlying type.
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if (const EnumType *EnumTy = Ty->getAs<EnumType>())
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Ty = EnumTy->getDecl()->getIntegerType();
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// All integral types are promoted to XLen width
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if (Size < XLen && Ty->isIntegralOrEnumerationType()) {
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return extendType(Ty);
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}
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if (const auto *EIT = Ty->getAs<BitIntType>()) {
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if (EIT->getNumBits() < XLen)
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return extendType(Ty);
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if (EIT->getNumBits() > 128 ||
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(!getContext().getTargetInfo().hasInt128Type() &&
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EIT->getNumBits() > 64))
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return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
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}
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return ABIArgInfo::getDirect();
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}
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if (const VectorType *VT = Ty->getAs<VectorType>())
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if (VT->getVectorKind() == VectorKind::RVVFixedLengthData ||
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VT->getVectorKind() == VectorKind::RVVFixedLengthMask)
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return coerceVLSVector(Ty);
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// Aggregates which are <= 2*XLen will be passed in registers if possible,
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// so coerce to integers.
|
||
if (Size <= 2 * XLen) {
|
||
unsigned Alignment = getContext().getTypeAlign(Ty);
|
||
|
||
// Use a single XLen int if possible, 2*XLen if 2*XLen alignment is
|
||
// required, and a 2-element XLen array if only XLen alignment is required.
|
||
if (Size <= XLen) {
|
||
return ABIArgInfo::getDirect(
|
||
llvm::IntegerType::get(getVMContext(), XLen));
|
||
} else if (Alignment == 2 * XLen) {
|
||
return ABIArgInfo::getDirect(
|
||
llvm::IntegerType::get(getVMContext(), 2 * XLen));
|
||
} else {
|
||
return ABIArgInfo::getDirect(llvm::ArrayType::get(
|
||
llvm::IntegerType::get(getVMContext(), XLen), 2));
|
||
}
|
||
}
|
||
return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
|
||
}
|
||
|
||
ABIArgInfo RISCVABIInfo::classifyReturnType(QualType RetTy) const {
|
||
if (RetTy->isVoidType())
|
||
return ABIArgInfo::getIgnore();
|
||
|
||
int ArgGPRsLeft = 2;
|
||
int ArgFPRsLeft = FLen ? 2 : 0;
|
||
|
||
// The rules for return and argument types are the same, so defer to
|
||
// classifyArgumentType.
|
||
return classifyArgumentType(RetTy, /*IsFixed=*/true, ArgGPRsLeft,
|
||
ArgFPRsLeft);
|
||
}
|
||
|
||
Address RISCVABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
|
||
QualType Ty) const {
|
||
CharUnits SlotSize = CharUnits::fromQuantity(XLen / 8);
|
||
|
||
// Empty records are ignored for parameter passing purposes.
|
||
if (isEmptyRecord(getContext(), Ty, true)) {
|
||
return Address(CGF.Builder.CreateLoad(VAListAddr),
|
||
CGF.ConvertTypeForMem(Ty), SlotSize);
|
||
}
|
||
|
||
auto TInfo = getContext().getTypeInfoInChars(Ty);
|
||
|
||
// TODO: To be compatible with GCC's behaviors, we force arguments with
|
||
// 2×XLEN-bit alignment and size at most 2×XLEN bits like `long long`,
|
||
// `unsigned long long` and `double` to have 4-byte alignment. This
|
||
// behavior may be changed when RV32E/ILP32E is ratified.
|
||
if (EABI && XLen == 32)
|
||
TInfo.Align = std::min(TInfo.Align, CharUnits::fromQuantity(4));
|
||
|
||
// Arguments bigger than 2*Xlen bytes are passed indirectly.
|
||
bool IsIndirect = TInfo.Width > 2 * SlotSize;
|
||
|
||
return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, TInfo,
|
||
SlotSize, /*AllowHigherAlign=*/true);
|
||
}
|
||
|
||
ABIArgInfo RISCVABIInfo::extendType(QualType Ty) const {
|
||
int TySize = getContext().getTypeSize(Ty);
|
||
// RV64 ABI requires unsigned 32 bit integers to be sign extended.
|
||
if (XLen == 64 && Ty->isUnsignedIntegerOrEnumerationType() && TySize == 32)
|
||
return ABIArgInfo::getSignExtend(Ty);
|
||
return ABIArgInfo::getExtend(Ty);
|
||
}
|
||
|
||
namespace {
|
||
class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
|
||
public:
|
||
RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen,
|
||
unsigned FLen, bool EABI)
|
||
: TargetCodeGenInfo(
|
||
std::make_unique<RISCVABIInfo>(CGT, XLen, FLen, EABI)) {}
|
||
|
||
void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
|
||
CodeGen::CodeGenModule &CGM) const override {
|
||
const auto *FD = dyn_cast_or_null<FunctionDecl>(D);
|
||
if (!FD) return;
|
||
|
||
const auto *Attr = FD->getAttr<RISCVInterruptAttr>();
|
||
if (!Attr)
|
||
return;
|
||
|
||
const char *Kind;
|
||
switch (Attr->getInterrupt()) {
|
||
case RISCVInterruptAttr::supervisor: Kind = "supervisor"; break;
|
||
case RISCVInterruptAttr::machine: Kind = "machine"; break;
|
||
}
|
||
|
||
auto *Fn = cast<llvm::Function>(GV);
|
||
|
||
Fn->addFnAttr("interrupt", Kind);
|
||
}
|
||
};
|
||
} // namespace
|
||
|
||
std::unique_ptr<TargetCodeGenInfo>
|
||
CodeGen::createRISCVTargetCodeGenInfo(CodeGenModule &CGM, unsigned XLen,
|
||
unsigned FLen, bool EABI) {
|
||
return std::make_unique<RISCVTargetCodeGenInfo>(CGM.getTypes(), XLen, FLen,
|
||
EABI);
|
||
}
|