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bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fma.mir
Sam Vervaeck 174b6f4d4e
Embed LLVM 18.1.8
2025-02-14 19:21:04 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -simplify-mir -aarch64-neon-syntax=apple -mattr=-fullfp16 -o - | FileCheck %s --check-prefix=NO-FP16
# RUN: llc %s -verify-machineinstrs -mtriple=aarch64-unknown-unknown -run-pass=legalizer -simplify-mir -aarch64-neon-syntax=apple -mattr=+fullfp16 -o - | FileCheck %s --check-prefix=FP16
...
---
name: test_v4f16.fma
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0, $d1, $d2
; NO-FP16-LABEL: name: test_v4f16.fma
; NO-FP16: liveins: $d0, $d1, $d2
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)
; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY1]](<4 x s16>)
; NO-FP16-NEXT: [[FPEXT2:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY2]](<4 x s16>)
; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT]], [[FPEXT1]], [[FPEXT2]]
; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA]](<4 x s32>)
; NO-FP16-NEXT: $d0 = COPY [[FPTRUNC]](<4 x s16>)
; NO-FP16-NEXT: RET_ReallyLR implicit $d0
;
; FP16-LABEL: name: test_v4f16.fma
; FP16: liveins: $d0, $d1, $d2
; FP16-NEXT: {{ $}}
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
; FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; FP16-NEXT: $d0 = COPY [[FMA]](<4 x s16>)
; FP16-NEXT: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = COPY $d1
%2:_(<4 x s16>) = COPY $d2
%3:_(<4 x s16>) = G_FMA %0, %1, %2
$d0 = COPY %3(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: test_v8f16.fma
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $q0, $q1, $q2
; NO-FP16-LABEL: name: test_v8f16.fma
; NO-FP16: liveins: $q0, $q1, $q2
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $q2
; NO-FP16-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
; NO-FP16-NEXT: [[UV2:%[0-9]+]]:_(<4 x s16>), [[UV3:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY1]](<8 x s16>)
; NO-FP16-NEXT: [[FPEXT2:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV2]](<4 x s16>)
; NO-FP16-NEXT: [[FPEXT3:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV3]](<4 x s16>)
; NO-FP16-NEXT: [[UV4:%[0-9]+]]:_(<4 x s16>), [[UV5:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY2]](<8 x s16>)
; NO-FP16-NEXT: [[FPEXT4:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV4]](<4 x s16>)
; NO-FP16-NEXT: [[FPEXT5:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV5]](<4 x s16>)
; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT]], [[FPEXT2]], [[FPEXT4]]
; NO-FP16-NEXT: [[FMA1:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT1]], [[FPEXT3]], [[FPEXT5]]
; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA]](<4 x s32>)
; NO-FP16-NEXT: [[FPTRUNC1:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA1]](<4 x s32>)
; NO-FP16-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[FPTRUNC]](<4 x s16>), [[FPTRUNC1]](<4 x s16>)
; NO-FP16-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<8 x s16>)
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
;
; FP16-LABEL: name: test_v8f16.fma
; FP16: liveins: $q0, $q1, $q2
; FP16-NEXT: {{ $}}
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $q2
; FP16-NEXT: [[FMA:%[0-9]+]]:_(<8 x s16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; FP16-NEXT: $q0 = COPY [[FMA]](<8 x s16>)
; FP16-NEXT: RET_ReallyLR implicit $q0
%0:_(<8 x s16>) = COPY $q0
%1:_(<8 x s16>) = COPY $q1
%2:_(<8 x s16>) = COPY $q2
%3:_(<8 x s16>) = G_FMA %0, %1, %2
$q0 = COPY %3(<8 x s16>)
RET_ReallyLR implicit $q0
...
---
name: test_v2f32.fma
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $d0, $d1, $d2
; NO-FP16-LABEL: name: test_v2f32.fma
; NO-FP16: liveins: $d0, $d1, $d2
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; NO-FP16-NEXT: $d0 = COPY [[FMA]](<2 x s32>)
; NO-FP16-NEXT: RET_ReallyLR implicit $d0
;
; FP16-LABEL: name: test_v2f32.fma
; FP16: liveins: $d0, $d1, $d2
; FP16-NEXT: {{ $}}
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
; FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; FP16-NEXT: $d0 = COPY [[FMA]](<2 x s32>)
; FP16-NEXT: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = COPY $d1
%2:_(<2 x s32>) = COPY $d2
%3:_(<2 x s32>) = G_FMA %0, %1, %2
$d0 = COPY %3(<2 x s32>)
RET_ReallyLR implicit $d0
...
---
name: test_v4f32.fma
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $q0, $q1, $q2
; NO-FP16-LABEL: name: test_v4f32.fma
; NO-FP16: liveins: $q0, $q1, $q2
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; NO-FP16-NEXT: $q0 = COPY [[FMA]](<4 x s32>)
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
;
; FP16-LABEL: name: test_v4f32.fma
; FP16: liveins: $q0, $q1, $q2
; FP16-NEXT: {{ $}}
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
; FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; FP16-NEXT: $q0 = COPY [[FMA]](<4 x s32>)
; FP16-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = COPY $q1
%2:_(<4 x s32>) = COPY $q2
%3:_(<4 x s32>) = G_FMA %0, %1, %2
$q0 = COPY %3(<4 x s32>)
RET_ReallyLR implicit $q0
...
---
name: test_v2f64.fma
alignment: 4
tracksRegLiveness: true
machineFunctionInfo: {}
body: |
bb.0:
liveins: $q0, $q1, $q2
; NO-FP16-LABEL: name: test_v2f64.fma
; NO-FP16: liveins: $q0, $q1, $q2
; NO-FP16-NEXT: {{ $}}
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; NO-FP16-NEXT: $q0 = COPY [[FMA]](<2 x s64>)
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
;
; FP16-LABEL: name: test_v2f64.fma
; FP16: liveins: $q0, $q1, $q2
; FP16-NEXT: {{ $}}
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
; FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
; FP16-NEXT: $q0 = COPY [[FMA]](<2 x s64>)
; FP16-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x s64>) = COPY $q0
%1:_(<2 x s64>) = COPY $q1
%2:_(<2 x s64>) = COPY $q2
%3:_(<2 x s64>) = G_FMA %0, %1, %2
$q0 = COPY %3(<2 x s64>)
RET_ReallyLR implicit $q0
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