bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AArch64/ptrauth-intrinsic-strip.ll
2025-02-14 19:21:04 +01:00

43 lines
1.2 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple arm64e-apple-darwin -verify-machineinstrs -global-isel=0 | FileCheck %s
; RUN: llc < %s -mtriple arm64e-apple-darwin -verify-machineinstrs -global-isel=1 -global-isel-abort=1 | FileCheck %s
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define i64 @test_strip_ia(i64 %arg) {
; CHECK-LABEL: test_strip_ia:
; CHECK: ; %bb.0:
; CHECK-NEXT: xpaci x0
; CHECK-NEXT: ret
%tmp = call i64 @llvm.ptrauth.strip(i64 %arg, i32 0)
ret i64 %tmp
}
define i64 @test_strip_ib(i64 %arg) {
; CHECK-LABEL: test_strip_ib:
; CHECK: ; %bb.0:
; CHECK-NEXT: xpaci x0
; CHECK-NEXT: ret
%tmp = call i64 @llvm.ptrauth.strip(i64 %arg, i32 1)
ret i64 %tmp
}
define i64 @test_strip_da(i64 %arg) {
; CHECK-LABEL: test_strip_da:
; CHECK: ; %bb.0:
; CHECK-NEXT: xpacd x0
; CHECK-NEXT: ret
%tmp = call i64 @llvm.ptrauth.strip(i64 %arg, i32 2)
ret i64 %tmp
}
define i64 @test_strip_db(i64 %arg) {
; CHECK-LABEL: test_strip_db:
; CHECK: ; %bb.0:
; CHECK-NEXT: xpacd x0
; CHECK-NEXT: ret
%tmp = call i64 @llvm.ptrauth.strip(i64 %arg, i32 3)
ret i64 %tmp
}
declare i64 @llvm.ptrauth.strip(i64, i32)