59 lines
2.5 KiB
TableGen
59 lines
2.5 KiB
TableGen
//=-HexagonScheduleV71T.td - Hexagon V71 Tiny Core Scheduling Definition ----=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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class HexagonV71TPseudoItin {
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list<InstrItinData> V71TPseudoItin_list = [
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InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT2, SLOT3]>], [2, 1, 1],
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[Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
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InstrStage<1, [SLOT2, SLOT3]>],
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[2, 1, 1],
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[Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>],
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[2, 1, 1]>,
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InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
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];
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}
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//
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// HVXItin contains some old itineraries still used by a handful of
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// instructions. Hopefully, we will be able to get rid of them soon.
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def HexagonV71TItinList : DepScalarItinV71T, DepHVXItinV71, HVXItin,
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HexagonV71TPseudoItin {
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list<InstrItinData> V71TItin_list = [
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InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0]>],
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[3, 1, 1],
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[Hex_FWD, Hex_FWD, Hex_FWD]>,
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InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0]>],
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[1, 1, 3, 3],
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[Hex_FWD, Hex_FWD]>
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];
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list<InstrItinData> ItinList =
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!listconcat(DepScalarItinV71T_list, V71TItin_list, DepHVXItinV71_list,
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HVXItin_list, V71TPseudoItin_list);
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}
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def HexagonItinerariesV71T :
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ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
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CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
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CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
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CVI_ALL_NOMEM, CVI_ZW],
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[Hex_FWD, HVX_FWD],
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HexagonV71TItinList.ItinList>;
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def HexagonModelV71T : SchedMachineModel {
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let IssueWidth = 3;
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let Itineraries = HexagonItinerariesV71T;
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let LoadLatency = 1;
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let CompleteModel = 0;
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}
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//===----------------------------------------------------------------------===//
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// Hexagon V71 Tiny Core Resource Definitions -
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//===----------------------------------------------------------------------===//
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