180 lines
6.8 KiB
TableGen
180 lines
6.8 KiB
TableGen
//===-- LoongArch.td - Describe the LoongArch Target -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// LoongArch subtarget features and instruction predicates.
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//===----------------------------------------------------------------------===//
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// LoongArch is divided into two versions, the 32-bit version (LA32) and the
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// 64-bit version (LA64).
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def Feature64Bit
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: SubtargetFeature<"64bit", "HasLA64", "true",
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"LA64 Basic Integer and Privilege Instruction Set">;
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def Feature32Bit
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: SubtargetFeature<"32bit", "HasLA32", "true",
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"LA32 Basic Integer and Privilege Instruction Set">;
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def IsLA64
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: Predicate<"Subtarget->is64Bit()">,
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AssemblerPredicate<(all_of Feature64Bit),
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"LA64 Basic Integer and Privilege Instruction Set">;
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def IsLA32
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: Predicate<"!Subtarget->is64Bit()">,
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AssemblerPredicate<(all_of(not Feature64Bit)),
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"LA32 Basic Integer and Privilege Instruction Set">;
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defvar LA32 = DefaultMode;
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def LA64 : HwMode<"+64bit", [IsLA64]>;
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// Single Precision floating point
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def FeatureBasicF
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: SubtargetFeature<"f", "HasBasicF", "true",
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"'F' (Single-Precision Floating-Point)">;
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def HasBasicF : Predicate<"Subtarget->hasBasicF()">;
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// Double Precision floating point
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def FeatureBasicD
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: SubtargetFeature<"d", "HasBasicD", "true",
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"'D' (Double-Precision Floating-Point)",
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[FeatureBasicF]>;
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def HasBasicD : Predicate<"Subtarget->hasBasicD()">;
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// Loongson SIMD eXtension (LSX)
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def FeatureExtLSX
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: SubtargetFeature<"lsx", "HasExtLSX", "true",
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"'LSX' (Loongson SIMD Extension)", [FeatureBasicD]>;
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def HasExtLSX : Predicate<"Subtarget->hasExtLSX()">;
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// Loongson Advanced SIMD eXtension (LASX)
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def FeatureExtLASX
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: SubtargetFeature<"lasx", "HasExtLASX", "true",
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"'LASX' (Loongson Advanced SIMD Extension)",
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[FeatureExtLSX]>;
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def HasExtLASX : Predicate<"Subtarget->hasExtLASX()">;
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// Loongson VirtualiZation (LVZ)
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def FeatureExtLVZ
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: SubtargetFeature<"lvz", "HasExtLVZ", "true",
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"'LVZ' (Loongson Virtualization Extension)">;
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def HasExtLVZ : Predicate<"Subtarget->hasExtLVZ()">;
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// Loongson Binary Translation (LBT)
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def FeatureExtLBT
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: SubtargetFeature<"lbt", "HasExtLBT", "true",
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"'LBT' (Loongson Binary Translation Extension)">;
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def HasExtLBT : Predicate<"Subtarget->hasExtLBT()">;
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// Expand la.global as la.pcrel
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def LaGlobalWithPcrel
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: SubtargetFeature<"la-global-with-pcrel", "HasLaGlobalWithPcrel", "true",
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"Expand la.global as la.pcrel">;
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def HasLaGlobalWithPcrel
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: Predicate<"Subtarget->hasLaGlobalWithPcrel()">,
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AssemblerPredicate<(all_of LaGlobalWithPcrel),
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"Expand la.global as la.pcrel">;
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// Expand la.global as la.abs
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def LaGlobalWithAbs
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: SubtargetFeature<"la-global-with-abs", "HasLaGlobalWithAbs", "true",
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"Expand la.global as la.abs">;
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def HasLaGlobalWithAbs
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: Predicate<"Subtarget->hasLaGlobalWithAbs()">,
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AssemblerPredicate<(all_of LaGlobalWithAbs),
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"Expand la.global as la.abs">;
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// Expand la.local as la.abs
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def LaLocalWithAbs
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: SubtargetFeature<"la-local-with-abs", "HasLaLocalWithAbs", "true",
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"Expand la.local as la.abs">;
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def HasLaLocalWithAbs
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: Predicate<"Subtarget->hasLaLocalWithAbs()">,
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AssemblerPredicate<(all_of LaLocalWithAbs),
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"Expand la.local as la.abs">;
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// Unaligned memory access
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def FeatureUAL
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: SubtargetFeature<"ual", "HasUAL", "true",
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"Allow memory accesses to be unaligned">;
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def FeatureRelax
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: SubtargetFeature<"relax", "HasLinkerRelax", "true",
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"Enable Linker relaxation">;
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// Experimental auto vectorization
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def FeatureAutoVec
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: SubtargetFeature<"auto-vec", "HasExpAutoVec", "true",
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"Experimental auto vectorization">;
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// Floating point approximation operation
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def FeatureFrecipe
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: SubtargetFeature<"frecipe", "HasFrecipe", "true",
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"Support frecipe.{s/d} and frsqrte.{s/d} instructions.">;
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def HasFrecipe : Predicate<"Subtarget->hasFrecipe()">;
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//===----------------------------------------------------------------------===//
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// Registers, instruction descriptions ...
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//===----------------------------------------------------------------------===//
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include "LoongArchRegisterInfo.td"
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include "LoongArchCallingConv.td"
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include "LoongArchInstrInfo.td"
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//===----------------------------------------------------------------------===//
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// LoongArch processors supported.
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//===----------------------------------------------------------------------===//
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def : ProcessorModel<"generic-la32", NoSchedModel, [Feature32Bit]>;
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def : ProcessorModel<"generic-la64", NoSchedModel, [Feature64Bit, FeatureUAL]>;
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// Generic 64-bit processor with double-precision floating-point support.
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def : ProcessorModel<"loongarch64", NoSchedModel, [Feature64Bit,
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FeatureUAL,
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FeatureBasicD]>;
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// Support generic for compatibility with other targets. The triple will be used
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// to change to the appropriate la32/la64 version.
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def : ProcessorModel<"generic", NoSchedModel, []>;
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def : ProcessorModel<"la464", NoSchedModel, [Feature64Bit,
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FeatureUAL,
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FeatureExtLASX,
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FeatureExtLVZ,
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FeatureExtLBT]>;
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//===----------------------------------------------------------------------===//
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// Define the LoongArch target.
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//===----------------------------------------------------------------------===//
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def LoongArchInstrInfo : InstrInfo {
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let guessInstructionProperties = 0;
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}
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def LoongArchAsmParser : AsmParser {
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let ShouldEmitMatchRegisterAltName = 1;
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let AllowDuplicateRegisterNames = 1;
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}
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def LoongArchAsmParserVariant : AsmParserVariant {
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int Variant = 0;
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// Recognize hard coded registers.
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string RegisterPrefix = "$";
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}
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def LoongArchAsmWriter : AsmWriter {
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int PassSubtarget = 1;
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}
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def LoongArch : Target {
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let InstructionSet = LoongArchInstrInfo;
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let AssemblyParsers = [LoongArchAsmParser];
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let AssemblyParserVariants = [LoongArchAsmParserVariant];
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let AssemblyWriters = [LoongArchAsmWriter];
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let AllowRegisterRenaming = 1;
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}
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