116 lines
4.5 KiB
C++
116 lines
4.5 KiB
C++
//=====-- NVPTXSubtarget.h - Define Subtarget for the NVPTX ---*- C++ -*--====//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the NVPTX specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXSUBTARGET_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTXSUBTARGET_H
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#include "NVPTX.h"
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#include "NVPTXFrameLowering.h"
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#include "NVPTXISelLowering.h"
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#include "NVPTXInstrInfo.h"
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#include "NVPTXRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "NVPTXGenSubtargetInfo.inc"
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namespace llvm {
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class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
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virtual void anchor();
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std::string TargetName;
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// PTX version x.y is represented as 10*x+y, e.g. 3.1 == 31
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unsigned PTXVersion;
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// Full SM version x.y is represented as 100*x+10*y+feature, e.g. 3.1 == 310
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// sm_90a == 901
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unsigned int FullSmVersion;
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// SM version x.y is represented as 10*x+y, e.g. 3.1 == 31. Derived from
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// FullSmVersion.
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unsigned int SmVersion;
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const NVPTXTargetMachine &TM;
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NVPTXInstrInfo InstrInfo;
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NVPTXTargetLowering TLInfo;
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SelectionDAGTargetInfo TSInfo;
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// NVPTX does not have any call stack frame, but need a NVPTX specific
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// FrameLowering class because TargetFrameLowering is abstract.
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NVPTXFrameLowering FrameLowering;
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public:
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/// This constructor initializes the data members to match that
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/// of the specified module.
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///
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NVPTXSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS, const NVPTXTargetMachine &TM);
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const TargetFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const NVPTXInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const NVPTXRegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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}
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const NVPTXTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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bool hasAtomAddF64() const { return SmVersion >= 60; }
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bool hasAtomScope() const { return SmVersion >= 60; }
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bool hasAtomBitwise64() const { return SmVersion >= 32; }
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bool hasAtomMinMax64() const { return SmVersion >= 32; }
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bool hasLDG() const { return SmVersion >= 32; }
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inline bool hasHWROT32() const { return SmVersion >= 32; }
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bool hasImageHandles() const;
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bool hasFP16Math() const { return SmVersion >= 53; }
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bool hasBF16Math() const { return SmVersion >= 80; }
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bool allowFP16Math() const;
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bool hasMaskOperator() const { return PTXVersion >= 71; }
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bool hasNoReturn() const { return SmVersion >= 30 && PTXVersion >= 64; }
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unsigned int getFullSmVersion() const { return FullSmVersion; }
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unsigned int getSmVersion() const { return getFullSmVersion() / 10; }
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// GPUs with "a" suffix have include architecture-accelerated features that
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// are supported on the specified architecture only, hence such targets do not
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// follow the onion layer model. hasAAFeatures() allows distinguishing such
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// GPU variants from the base GPU architecture.
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// - 0 represents base GPU model,
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// - non-zero value identifies particular architecture-accelerated variant.
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bool hasAAFeatures() const { return getFullSmVersion() % 10; }
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std::string getTargetName() const { return TargetName; }
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// Get maximum value of required alignments among the supported data types.
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// From the PTX ISA doc, section 8.2.3:
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// The memory consistency model relates operations executed on memory
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// locations with scalar data-types, which have a maximum size and alignment
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// of 64 bits. Memory operations with a vector data-type are modelled as a
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// set of equivalent memory operations with a scalar data-type, executed in
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// an unspecified order on the elements in the vector.
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unsigned getMaxRequiredAlignment() const { return 8; }
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unsigned getPTXVersion() const { return PTXVersion; }
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NVPTXSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
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void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
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};
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} // End llvm namespace
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#endif
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