315 lines
15 KiB
TableGen
315 lines
15 KiB
TableGen
//===-- PPCScheduleP7.td - PPC P7 Scheduling Definitions ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the SchedModel for the POWER7 processor.
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//
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//===----------------------------------------------------------------------===//
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def P7Model : SchedMachineModel {
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let IssueWidth = 6; // 4 (non-branch) instructions are dispatched per cycle.
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// Note that the dispatch bundle size is 6 (including
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// branches), but the total internal issue bandwidth per
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// cycle (from all queues) is 8.
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let LoadLatency = 3; // Optimistic load latency assuming bypass.
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// This is overriden by OperandCycles if the
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// Itineraries are queried instead.
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let MispredictPenalty = 16;
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let MicroOpBufferSize = 44;
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// Try to make sure we have at least 10 dispatch groups in a loop.
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let LoopMicroOpBufferSize = 40;
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let CompleteModel = 0;
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let UnsupportedFeatures = [HasSPE, PrefixInstrs, MMA,
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PairedVectorMemops, IsISA3_0, IsISA2_07,
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PCRelativeMemops, IsISA3_1, IsISAFuture];
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}
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let SchedModel = P7Model in {
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def P7_LSU_FXU: ProcResource<4>;
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def P7_LSU: ProcResource<2> {
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let Super = P7_LSU_FXU;
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}
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def P7_FXU: ProcResource<2> {
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let Super = P7_LSU_FXU;
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}
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// Implemented as two 2-way SIMD operations for double- and single-precision.
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def P7_FPU: ProcResource<4>;
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// Scalar binary floating point instructions can only use two FPUs.
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def P7_ScalarFPU: ProcResource<2> {
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let Super = P7_FPU;
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}
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def P7_VectorFPU: ProcResource<2> {
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let Super = P7_FPU;
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}
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// Executing simple FX, complex FX, permute and 4-way SIMD single-precision FP ops
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def P7_VMX: ProcResource<1>;
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def P7_VPM: ProcResource<1> {
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let Super = P7_VMX;
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let BufferSize = 1;
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}
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def P7_VXS: ProcResource<1> {
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let Super = P7_VMX;
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}
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def P7_DFU: ProcResource<1>;
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def P7_BRU: ProcResource<1>;
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def P7_CRU: ProcResource<1>;
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def P7_PORT_LS : ProcResource<2>;
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def P7_PORT_FX : ProcResource<2>;
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def P7_PORT_FP : ProcResource<2>;
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def P7_PORT_BR : ProcResource<1>;
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def P7_PORT_CR : ProcResource<1>;
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def P7_DISP_LS : SchedWriteRes<[P7_PORT_LS]>;
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def P7_DISP_FX : SchedWriteRes<[P7_PORT_FX]>;
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def P7_DISP_FP : SchedWriteRes<[P7_PORT_FP]>;
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def P7_DISP_BR : SchedWriteRes<[P7_PORT_BR]>;
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def P7_DISP_CR : SchedWriteRes<[P7_PORT_CR]>;
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def P7_BRU_NONE : SchedWriteRes<[P7_BRU]>;
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def P7_BRU_3C : SchedWriteRes<[P7_BRU]> { let Latency = 3; }
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def P7_BRU_4C : SchedWriteRes<[P7_BRU]> { let Latency = 4; }
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def P7_CRU_NONE : SchedWriteRes<[P7_CRU]>;
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def P7_CRU_3C : SchedWriteRes<[P7_CRU]> { let Latency = 3; }
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def P7_CRU_6C : SchedWriteRes<[P7_CRU]> { let Latency = 6; }
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def P7_LSU_NONE : SchedWriteRes<[P7_LSU]>;
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def P7_LSU_2C : SchedWriteRes<[P7_LSU]> { let Latency = 2; }
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def P7_LSU_3C : SchedWriteRes<[P7_LSU]> { let Latency = 3; }
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def P7_LSU_4C : SchedWriteRes<[P7_LSU]> { let Latency = 4; }
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def P7_FXU_NONE : SchedWriteRes<[P7_FXU]>;
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def P7_FXU_2C : SchedWriteRes<[P7_FXU]> { let Latency = 2; }
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def P7_FXU_3C : SchedWriteRes<[P7_FXU]> { let Latency = 3; }
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def P7_FXU_4C : SchedWriteRes<[P7_FXU]> { let Latency = 4; }
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def P7_FXU_5C : SchedWriteRes<[P7_FXU]> { let Latency = 5; }
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def P7_FXU_38C : SchedWriteRes<[P7_FXU]> { let Latency = 38; }
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def P7_FXU_69C : SchedWriteRes<[P7_FXU]> { let Latency = 69; }
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def P7_LSU_FXU_2C : SchedWriteRes<[P7_LSU_FXU]> { let Latency = 2; }
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def P7_FPU_NONE : SchedWriteRes<[P7_FPU]>;
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def P7_VectorFPU_6C : SchedWriteRes<[P7_VectorFPU]> { let Latency = 6; }
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def P7_VectorFPU_25C : SchedWriteRes<[P7_VectorFPU]> { let Latency = 25; }
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def P7_VectorFPU_30C : SchedWriteRes<[P7_VectorFPU]> { let Latency = 30; }
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def P7_VectorFPU_31C : SchedWriteRes<[P7_VectorFPU]> { let Latency = 31; }
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def P7_VectorFPU_42C : SchedWriteRes<[P7_VectorFPU]> { let Latency = 42; }
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def P7_ScalarFPU_6C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 6; }
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def P7_ScalarFPU_8C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 8; }
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def P7_ScalarFPU_27C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 27; }
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def P7_ScalarFPU_31C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 31; }
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def P7_ScalarFPU_32C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 32; }
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def P7_ScalarFPU_33C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 33; }
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def P7_ScalarFPU_42C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 42; }
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def P7_ScalarFPU_44C : SchedWriteRes<[P7_ScalarFPU]> { let Latency = 44; }
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def P7_VXS_2C : SchedWriteRes<[P7_VXS]> { let Latency = 2; }
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def P7_VPM_3C : SchedWriteRes<[P7_VPM]> { let Latency = 3; }
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// Instruction of BRU pipeline
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def : InstRW<[P7_BRU_NONE, P7_DISP_BR],
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(instregex "^B(L)?(A)?(8)?(_NOP|_NOTOC)?(_TLS|_RM)?(_)?$")>;
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def : InstRW<[P7_BRU_3C, P7_DISP_BR], (instrs
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BDZLRLp, BDZLRm, BDZLRp, BDZLm, BDZLp, BDZm, BDZp,
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BDNZ, BDNZ8, BDNZA, BDNZAm, BDNZAp, BDNZL, BDNZLA, BDNZLAm, BDNZLAp, BDNZLR,
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BDNZLR8, BDNZLRL, BDNZLRLm, BDNZLRLp, BDNZLRm, BDNZLRp, BDNZLm, BDNZLp,
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BDNZm, BDNZp, BDZ, BDZ8, BDZA, BDZAm, BDZAp, BDZL, BDZLA, BDZLAm, BDZLAp,
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BDZLR, BDZLR8, BDZLRL, BDZLRLm, BLR, BLR8, BLRL, BCL, BCLR, BCLRL, BCLRLn,
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BCLRn, BCLalways, BCLn, BCTR, BCTR8, BCTRL, BCTRL8, BCTRL8_LDinto_toc,
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BCTRL8_LDinto_toc_RM, BCTRL8_RM, BCTRL_LWZinto_toc, BCTRL_LWZinto_toc_RM,
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BCTRL_RM, BCn, BC, BCC, BCCA, BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL,
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BCCLA, BCCLR, BCCLRL, BCCTR, BCCTR8, BCCTR8n, BCCTRL, BCCTRL8,
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BCCCTR, BCCCTR8, BCCCTRL, BCCCTRL8, BCCL, BCCLA, BCCLR, BCCLRL, BCCTR,
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BCCTR8, BCCTR8n, BCCTRL, BCCTRL8, BCCTRL8n, BCCTRLn, BCCTRn, gBC, gBCA,
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gBCAat, gBCCTR, gBCCTRL, gBCL, gBCLA, gBCLAat, gBCLR, gBCLRL, gBCLat, gBCat,
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MFCTR, MFCTR8, MFLR, MFLR8
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)>;
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def : InstRW<[P7_BRU_4C], (instrs MTLR, MTLR8, MTCTR, MTCTR8, MTCTR8loop, MTCTRloop)>;
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// Instructions of CRU pipeline
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def : InstRW<[P7_CRU_NONE], (instrs MFCR, MFCR8)>;
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def : InstRW<[P7_CRU_3C], (instrs MCRF)>;
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def : InstRW<[P7_CRU_6C, P7_DISP_CR], (instrs
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CR6SET, CR6UNSET, CRSET, CRUNSET,
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CRAND, CRANDC, CREQV, CRNAND, CRNOR, CRNOT, CROR, CRORC
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)>;
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// Instructions of LSU and FXU pipelines
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def : InstRW<[P7_LSU_NONE, P7_DISP_LS], (instrs LMW, LWARX, LWARXL, LDARX, LDARXL)>;
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def : InstRW<[P7_LSU_2C, P7_DISP_LS], (instrs LHBRX, LHBRX8, LWBRX, LWBRX8)>;
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def : InstRW<[P7_LSU_3C], (instrs MFSR, MFSRIN)>;
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def : InstRW<[P7_LSU_3C, P7_DISP_LS], (instrs
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LFS, LFSX, LFSXTLS, LFSXTLS_, LFD, LFDX, LFDXTLS, LFDXTLS_, LXSDX, LXVD2X,
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LXVW4X, LXVDSX
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)>;
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def : InstRW<[P7_LSU_3C, P7_FXU_3C, P7_DISP_LS], (instrs
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LFSU, LFSUX, LFDU, LFDUX)>;
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def : InstRW<[P7_LSU_NONE, P7_FPU_NONE, P7_DISP_LS], (instrs
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STXSDX, STXVD2X, STXVW4X)>;
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def : InstRW<[P7_LSU_4C, P7_FXU_4C, P7_DISP_LS], (instrs
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LBARX, LBZCIX, LDBRX, LDCIX, LFIWAX, LFIWZX, LHARX, LHZCIX, LSWI, LVEBX,
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LVEHX, LVEWX, LVSL, LVSR, LVX, LVXL, LWZCIX,
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STFD, STFDU, STFDUX, STFDX, STFIWX, STFS, STFSU, STFSUX, STFSX,
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STHCIX, STSWI, STVEBX, STVEHX, STVEWX, STVX, STVXL, STWCIX,
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LHA, LHA8, LHAX, LHAX8, LWA, LWAX, LWAX_32, LWA_32, LHAU, LHAU8,
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LHAUX, LHAUX8, LWAUX
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)>;
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def : InstRW<[P7_LSU_NONE, P7_FXU_NONE, P7_DISP_LS], (instrs
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STB, STB8, STH, STH8, STW, STW8, STD, STBX, STBX8, STHX, STHX8, STWX,
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STWX8, STDX, STHBRX, STWBRX, STMW, STWCX, STDCX, STDU, STHU, STHU8,
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STBU, STBU8, STWU, STWU8, STDUX, STWUX, STWUX8, STHUX, STHUX8, STBUX, STBUX8
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)>;
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def : InstRW<[P7_LSU_2C, P7_FXU_2C, P7_DISP_LS], (instrs
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LWZU, LWZU8, LHZU, LHZU8, LBZU, LBZU8, LDU,
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LWZUX, LWZUX8, LHZUX, LHZUX8, LBZUX, LBZUX8, LDUX
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)>;
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def : InstRW<[P7_LSU_FXU_2C, P7_DISP_FX], (instrs
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(instregex "^(ADD|L)I(S)?(8)?$"),
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(instregex "^(ADD|SUBF)(4|8)(TLS)?(_)?(_rec)?$"),
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(instregex "^(X)?ORI(S)?(8)?$"),
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(instregex "^(X)OR(8)?(_rec)?$"),
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ADDIC, ADDIC8, SUBFIC, SUBFIC8, SUBFZE, SUBFZE8,
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ADDE, ADDE8, ADDME, ADDME8, SUBFME, SUBFME8,
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NEG, NEG8, NEG8_rec, NEG_rec, NEG8O, NEGO,
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ANDI_rec, ANDIS_rec, AND, AND8, AND_rec, AND8_rec,
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NAND, NAND8, NAND_rec, NAND8_rec, NOR, NOR8, NOR_rec, NOR8_rec,
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EQV, EQV8, EQV_rec, EQV8_rec, ANDC, ANDC8, ANDC_rec, ANDC8_rec,
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ORC, ORC8, ORC_rec, ORC8_rec
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)>;
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def : InstRW<[P7_FXU_2C, P7_DISP_FX], (instrs
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CMPD, CMPDI, CMPLD, CMPLDI, CMPLW, CMPLWI, CMPW, CMPWI,
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EXTSB8_32_64, EXTSB8_rec, EXTSH8_32_64, EXTSH8_rec, EXTSW_32,
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EXTSW_32_64, EXTSW_32_64_rec, POPCNTB, POPCNTB8, POPCNTD, POPCNTW,
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ADDPCIS, ANDI8_rec, ANDIS8_rec, SUBFUS, SUBFUS_rec,
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ADD4O, ADD8O, ADDC, ADDC8, SUBFO, SUBF8O, SUBFC, SUBFC8,
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ADDIC_rec, ADDE8_rec, ADDE_rec, SUBFE8_rec, SUBFE_rec,
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ADDME8_rec, ADDME_rec, SUBFME8_rec, SUBFME_rec, ADDZE8_rec, ADDZE_rec,
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SUBFZE_rec, SUBFZE8_rec, ADD8O_rec, SUBFO_rec, SUBF8O_rec, ADD4O_rec,
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ADD8O_rec, SUBF8O_rec, SUBFO_rec, ADDE8O, ADDEO, SUBFE8O, SUBFEO, ADDME8O,
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ADDMEO, SUBFME8O, SUBFMEO, ADDZE8O, ADDZEO, SUBFZE8O, SUBFZEO, NEG8O_rec,
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NEGO_rec, ADDEO, ADDE8O, SUBFEO, SUBFE8O, ADDMEO, SUBFMEO, SUBFME8O, ADDME8O,
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ADDZEO, ADDZE8O, SUBFZEO, SUBFZE8O, NEG8O_rec, NEGO_rec,
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ADDE8O_rec, ADDEO_rec, ADDMEO_rec, ADDME8O_rec, SUBFMEO_rec, SUBFME8O_rec,
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ADDZEO_rec, ADDZE8O_rec, SUBFZEO_rec, SUBFZE8O_rec,
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ADDC8_rec, ADDC_rec, ADDCO, ADDCO_rec, ADDC8O, ADDC8O_rec,
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SUBFC8_rec, SUBFC_rec, SUBFCO, SUBFC8O, SUBFCO_rec, SUBFC8O_rec,
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EXTSB, EXTSB8, EXTSB_rec, EXTSH, EXTSH8, EXTSH_rec, EXTSW, EXTSW_rec,
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RLDICL, RLDICL_rec, RLDICR, RLDICR_rec, RLDIC, RLDIC_rec,
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RLWINM, RLWINM8, RLWINM_rec, RLDCL, RLDCL_rec, RLDCR, RLDCR_rec,
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RLWNM, RLWNM8, RLWNM_rec, RLDIMI, RLDIMI_rec,
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RLDICL_32, RLDICL_32_64, RLDICL_32_rec, RLDICR_32, RLWINM8_rec, RLWNM8_rec,
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SLD, SLD_rec, SLW, SLW8, SLW_rec, SLW8_rec, SRD, SRD_rec, SRW, SRW8, SRW_rec,
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SRW8_rec, SRADI, SRADI_rec, SRAWI, SRAWI_rec, SRAD, SRAD_rec, SRAW, SRAW_rec,
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SRADI_32, SUBFE, SUBFE8, SUBFE8O_rec, SUBFEO_rec
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)>;
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def : InstRW<[P7_FXU_3C, P7_DISP_FX], (instregex "^CNT(L|T)Z(D|W)(8)?(M)?(_rec)?$")>;
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def : InstRW<[P7_FXU_5C, P7_DISP_FX], (instrs
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MULLI, MULLI8, MULLW, MULHW, MULHWU, MULLD, MULHD, MULHDU, MULLWO, MULLDO,
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MULLW_rec, MULLD_rec, MULHD_rec, MULHW_rec, MULHDU_rec, MULHWU_rec, MULLWO_rec,
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MULLDO_rec
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)>;
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def : InstRW<[P7_FXU_38C, P7_DISP_FX], (instrs
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DIVDE, DIVDEO, DIVDEO_rec, DIVDEU, DIVDEUO, DIVDEUO_rec, DIVDEU_rec, DIVDE_rec,
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DIVWE, DIVWEO, DIVWEO_rec, DIVWEU, DIVWEUO, DIVWEUO_rec, DIVWEU_rec, DIVWE_rec,
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DIVW, DIVWU, DIVWU_rec, DIVWO, DIVWO_rec, DIVWUO, DIVWUO_rec, DIVW_rec
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)>;
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def : InstRW<[P7_FXU_69C, P7_DISP_FX], (instrs
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DIVD, DIVDU, DIVDO, DIVDO_rec, DIVDUO, DIVDUO_rec, DIVDU_rec, DIVD_rec)>;
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// Instructions of FPU and VMX pipeline
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def : InstRW<[P7_ScalarFPU_6C, P7_DISP_FP], (instrs
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(instregex "^F(N)?(M)?(R|ADD|SUB|ABS|NEG|NABS|UL)(D|S)?(_rec)?$"),
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(instregex "^FC(T|F)I(D|W)(U)?(S)?(Z)?(_rec)?$"),
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(instregex "^XS(N)?M(SUB|ADD)(A|M)(D|S)P$"),
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(instregex "^XS(NEG|ABS|NABS|ADD|SUB|MUL)(D|S)P(s)?$"),
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FRE, FRES_rec, FRE_rec, FRSP_rec, FTDIV, FTSQRT,
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FRSP, FRES, FRSQRTE, FRSQRTES, FRSQRTES_rec, FRSQRTE_rec, FSELD, FSELS,
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FSELD_rec, FSELS_rec, FCPSGND, FCPSGND_rec, FCPSGNS, FCPSGNS_rec,
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FRIMD, FRIMD_rec, FRIMS, FRIMS_rec, FRIND, FRIND_rec, FRINS, FRINS_rec,
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FRIPD, FRIPD_rec, FRIPS, FRIPS_rec, FRIZD, FRIZD_rec, FRIZS, FRIZS_rec,
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XSCPSGNDP, XSCVDPSP, XSCVDPSXDS, XSCVDPSXDSs, XSCVDPSXWS, XSCVDPSXWSs,
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XSCVDPUXDS, XSCVDPUXDSs, XSCVDPUXWS, XSCVDPUXWSs, XSCVSPDP, XSCVSXDDP,
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XSCVUXDDP, XSMAXDP, XSMINDP, XSRDPI, XSRDPIC, XSRDPIM, XSRDPIP, XSRDPIZ,
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XSREDP, XSRSQRTEDP, XSTDIVDP, XSTSQRTDP, XSCMPODP, XSCMPUDP
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)>;
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def : InstRW<[P7_VectorFPU_6C, P7_DISP_FP], (instrs
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(instregex "^XV(N)?(M)?(ADD|SUB)(A|M)?(D|S)P$"),
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(instregex "^XV(MAX|MIN|MUL|NEG|ABS|ADD|NABS)(D|S)P$"),
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XVCMPEQDP, XVCMPEQDP_rec, XVCMPGEDP, XVCMPGEDP_rec, XVCMPGTDP, XVCMPGTDP_rec,
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XVCPSGNDP, XVCVDPSXDS, XVCVDPSXWS, XVCVDPUXDS, XVCVDPUXWS, XVCVSPSXDS,
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XVCVSPSXWS, XVCVSPUXDS, XVCVSPUXWS, XVCVSXDDP, XVCVSXWDP, XVCVUXDDP,
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XVCVUXWDP, XVRDPI, XVRDPIC, XVRDPIM, XVRDPIP, XVRDPIZ, XVREDP,
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XVRSPI, XVRSPIC, XVRSPIM, XVRSPIP, XVRSPIZ, XVRSQRTEDP, XVTDIVDP,
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XVTSQRTDP
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)>;
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// TODO: Altivec instructions are not listed in Book IV.
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def : InstRW<[P7_VPM_3C, P7_DISP_FP], (instrs
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(instregex "^VPK(S|U)(H|W)(S|U)(S|M)$"),
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(instregex "^VUPK(H|L)(S|P)(X|B|H)$"),
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VPERM, XXMRGHW, XXMRGLW, XXPERMDI, XXPERMDIs, XXSLDWI, XXSLDWIs,
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VSPLTB, VSPLTBs, VSPLTH, VSPLTHs, VSPLTISB, VSPLTISH, VSPLTISW, VSPLTW,
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XXSPLTW, XXSPLTWs, VSEL, XXSEL, VPKPX
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)>;
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def : InstRW<[P7_VXS_2C, P7_DISP_FP], (instrs
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(instregex "^VADD(U|S)(B|H|W)(S|M)$"),
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(instregex "^V(MAX|MIN)(S|U)(B|H|W)$"),
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(instregex "^V(MRG)(L|H)(B|H|W)$"),
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XXLORf, XXLXORdpz, XXLXORspz, XXLXORz, XVRSQRTESP, XVRESP,
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XVTDIVSP, XVTSQRTSP, XVCMPEQSP, XVCMPEQSP_rec, XVCMPGESP, XVCMPGESP_rec,
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XVCMPGTSP, XVCMPGTSP_rec, XVCVSXDSP, XVCVSXWSP, XVCVUXDSP, XVCVUXWSP,
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XVCPSGNSP, XVCVDPSP, VADDCUW, VADDFP, VAND, VANDC, VAVGSB, VAVGSH,
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VAVGSW, VAVGUB, VAVGUH, VAVGUW, VCFSX, VCFUX, VCMPBFP, VCMPBFP_rec,
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VCMPEQFP, VCMPEQFP_rec, VCMPEQUB, VCMPEQUB_rec, VCMPEQUH, VCMPEQUH_rec,
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VCMPEQUW, VCMPEQUW_rec, VCMPGEFP, VCMPGEFP_rec, VCMPGTFP, VCMPGTFP_rec,
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VCMPGTSB, VCMPGTSB_rec, VCMPGTSH, VCMPGTSH_rec, VCMPGTSW, VCMPGTSW_rec,
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VCMPGTUB, VCMPGTUB_rec, VCMPGTUH, VCMPGTUH_rec, VCMPGTUW, VCMPGTUW_rec,
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VCTSXS, VCTUXS, VEXPTEFP, VLOGEFP, VNOR, VOR,
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VMADDFP, VMHADDSHS, VMHRADDSHS, VMLADDUHM, VNMSUBFP, VMAXFP, VMINFP,
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VMSUMMBM, VMSUMSHM, VMSUMSHS, VMSUMUBM, VMSUMUDM, VMSUMUHM, VMSUMUHS,
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VMULESB, VMULESH, VMULEUB, VMULEUH, VMULOSB, VMULOSH, VMULOUB, VMULOUH,
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VREFP, VRFIM, VRFIN, VRFIP, VRFIZ, VRLB, VRLH, VRLW, VRSQRTEFP,
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VSR, VSRAB, VSRAH, VSRAW, VSRB, VSRH, VSRO, VSRW, VSUBCUW, VSL, VSLB,
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VSLDOI, VSLH, VSLO, VSLW, VSUBFP, VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBM,
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VSUBUBS, VSUBUHM, VSUBUHS, VSUBUWM, VSUBUWS, VSUM2SWS, VSUM4SBS, VSUM4SHS,
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VSUM4UBS, VSUMSWS, VXOR, XXLAND, XXLANDC, XXLNOR, XXLOR, XXLXOR
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)>;
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def : InstRW<[P7_ScalarFPU_8C, P7_DISP_FP],
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(instrs FCMPOD, FCMPOS, FCMPUD, FCMPUS)>;
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def : InstRW<[P7_ScalarFPU_27C, P7_DISP_FP], (instrs FDIVS, FDIVS_rec)>;
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def : InstRW<[P7_ScalarFPU_31C, P7_DISP_FP], (instrs XSDIVDP)>;
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def : InstRW<[P7_ScalarFPU_32C, P7_DISP_FP], (instrs FSQRTS, XSSQRTSP, FSQRTS_rec)>;
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def : InstRW<[P7_ScalarFPU_33C, P7_DISP_FP], (instrs FDIV, FDIV_rec)>;
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def : InstRW<[P7_ScalarFPU_42C, P7_DISP_FP], (instrs XSSQRTDP)>;
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def : InstRW<[P7_ScalarFPU_44C, P7_DISP_FP], (instrs FSQRT, FSQRT_rec)>;
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def : InstRW<[P7_VectorFPU_25C, P7_DISP_FP], (instrs XVDIVSP)>;
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def : InstRW<[P7_VectorFPU_30C, P7_DISP_FP], (instrs XVSQRTSP)>;
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def : InstRW<[P7_VectorFPU_31C, P7_DISP_FP], (instrs XVDIVDP)>;
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def : InstRW<[P7_VectorFPU_42C, P7_DISP_FP], (instrs XVSQRTDP)>;
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}
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