199 lines
6 KiB
TableGen
199 lines
6 KiB
TableGen
//===-------------- VVPInstrInfo.td - VVP_* SDNode patterns ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the VE Vector Predicated SDNodes (VVP SDNodes). VVP
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// SDNodes are an intermediate isel layer between the vector SDNodes emitted by
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// LLVM and the actual VE vector instructions. For example:
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//
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// ADD(x,y) --> VVP_ADD(x,y,mask,evl) --> VADDSWSXrvml(x,y,mask,evl)
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// ^ ^ ^
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// The standard The VVP layer SDNode. The VE vector instruction.
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// SDNode.
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//
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// TODO explain how VVP nodes relate to VP SDNodes once VP ISel is uptream.
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//===----------------------------------------------------------------------===//
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// vvp_load(ptr, stride, mask, avl)
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def SDTLoadVVP : SDTypeProfile<1, 4, [
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SDTCisVec<0>,
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SDTCisPtrTy<1>,
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SDTCisInt<2>,
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SDTCisVec<3>,
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IsVLVT<4>
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]>;
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// vvp_store(data, ptr, stride, mask, avl)
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def SDTStoreVVP: SDTypeProfile<0, 5, [
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SDTCisVec<0>,
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SDTCisPtrTy<1>,
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SDTCisInt<2>,
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SDTCisVec<3>,
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IsVLVT<4>
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]>;
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// vvp_scatter(chain, data, addr, mask, avl)
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def SDTScatterVVP: SDTypeProfile<0, 4, [
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SDTCisVec<0>,
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SDTCisVec<1>,
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SDTCisVec<2>,
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SDTCisSameNumEltsAs<0, 2>,
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IsVLVT<3>
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]>;
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// vvp_gather(chain, addr, mask, avl)
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def SDTGatherVVP: SDTypeProfile<1, 3, [
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SDTCisVec<0>,
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SDTCisVec<1>,
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SDTCisSameNumEltsAs<0, 2>,
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IsVLVT<3>
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]>;
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// BinaryOp(x,y,mask,vl)
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def SDTIntBinOpVVP : SDTypeProfile<1, 4, [ // vp_add, vp_and, etc.
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SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCisInt<0>,
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SDTCisSameNumEltsAs<0, 3>,
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IsVLVT<4>
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]>;
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// UnaryFPOp(x,mask,vl)
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def SDTFPUnaryOpVVP : SDTypeProfile<1, 3, [
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SDTCisSameAs<0, 1>,
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SDTCisFP<0>,
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SDTCisInt<2>,
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SDTCisSameNumEltsAs<0, 2>,
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IsVLVT<3>
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]>;
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// BinaryFPOp(x,y,mask,vl)
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def SDTFPBinOpVVP : SDTypeProfile<1, 4, [ // vvp_fadd, etc.
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SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCisFP<0>,
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SDTCisInt<3>,
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SDTCisSameNumEltsAs<0, 3>,
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IsVLVT<4>
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]>;
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// TernaryFPOp(x,y,z,mask,vl)
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def SDTFPTernaryOpVVP : SDTypeProfile<1, 5, [
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SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCisSameAs<0, 3>,
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SDTCisFP<0>,
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SDTCisInt<4>,
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SDTCisSameNumEltsAs<0, 4>,
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IsVLVT<5>
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]>;
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// Select(OnTrue, OnFalse, SelMask, vl)
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def SDTSelectVVP : SDTypeProfile<1, 4, [ // vp_select, vp_merge
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SDTCisVec<0>,
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SDTCisSameNumEltsAs<0, 3>,
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SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>,
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IsVLVT<4>
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]>;
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// SetCC (lhs, rhs, cc, mask, vl)
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def SDTSetCCVVP : SDTypeProfile<1, 5, [ // vp_setcc
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SDTCisVec<0>,
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SDTCisVec<1>,
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SDTCisSameNumEltsAs<0, 1>,
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SDTCisSameAs<1, 2>,
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SDTCisVT<3, OtherVT>,
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SDTCisInt<4>,
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SDTCisSameNumEltsAs<0, 4>,
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IsVLVT<5>
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]>;
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// vvp_reduce(vector, mask, vl)
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def SDTReduceVVP : SDTypeProfile<1, 3, [
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SDTCisVec<1>,
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SDTCisInt<2>,
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SDTCisVec<2>,
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SDTCisSameNumEltsAs<1,2>,
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IsVLVT<3>
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]>;
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// Binary operator commutative pattern.
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class vvp_commutative<SDNode RootOp> :
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PatFrags<
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(ops node:$lhs, node:$rhs, node:$mask, node:$vlen),
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[(RootOp node:$lhs, node:$rhs, node:$mask, node:$vlen),
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(RootOp node:$rhs, node:$lhs, node:$mask, node:$vlen)]>;
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class vvp_fma_commutative<SDNode RootOp> :
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PatFrags<
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(ops node:$X, node:$Y, node:$Z, node:$mask, node:$vlen),
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[(RootOp node:$X, node:$Y, node:$Z, node:$mask, node:$vlen),
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(RootOp node:$X, node:$Z, node:$Y, node:$mask, node:$vlen)]>;
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// VVP node definitions.
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def vvp_add : SDNode<"VEISD::VVP_ADD", SDTIntBinOpVVP>;
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def c_vvp_add : vvp_commutative<vvp_add>;
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def vvp_sub : SDNode<"VEISD::VVP_SUB", SDTIntBinOpVVP>;
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def vvp_mul : SDNode<"VEISD::VVP_MUL", SDTIntBinOpVVP>;
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def c_vvp_mul : vvp_commutative<vvp_mul>;
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def vvp_sdiv : SDNode<"VEISD::VVP_SDIV", SDTIntBinOpVVP>;
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def vvp_udiv : SDNode<"VEISD::VVP_UDIV", SDTIntBinOpVVP>;
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def vvp_and : SDNode<"VEISD::VVP_AND", SDTIntBinOpVVP>;
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def c_vvp_and : vvp_commutative<vvp_and>;
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def vvp_or : SDNode<"VEISD::VVP_OR", SDTIntBinOpVVP>;
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def c_vvp_or : vvp_commutative<vvp_or>;
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def vvp_xor : SDNode<"VEISD::VVP_XOR", SDTIntBinOpVVP>;
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def c_vvp_xor : vvp_commutative<vvp_xor>;
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def vvp_srl : SDNode<"VEISD::VVP_SRL", SDTIntBinOpVVP>;
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def vvp_sra : SDNode<"VEISD::VVP_SRA", SDTIntBinOpVVP>;
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def vvp_shl : SDNode<"VEISD::VVP_SHL", SDTIntBinOpVVP>;
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def vvp_fneg : SDNode<"VEISD::VVP_FNEG", SDTFPUnaryOpVVP>;
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def vvp_fadd : SDNode<"VEISD::VVP_FADD", SDTFPBinOpVVP>;
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def c_vvp_fadd : vvp_commutative<vvp_fadd>;
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def vvp_fsub : SDNode<"VEISD::VVP_FSUB", SDTFPBinOpVVP>;
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def vvp_fmul : SDNode<"VEISD::VVP_FMUL", SDTFPBinOpVVP>;
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def c_vvp_fmul : vvp_commutative<vvp_fmul>;
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def vvp_fdiv : SDNode<"VEISD::VVP_FDIV", SDTFPBinOpVVP>;
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def vvp_ffma : SDNode<"VEISD::VVP_FFMA", SDTFPTernaryOpVVP>;
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def c_vvp_ffma : vvp_fma_commutative<vvp_ffma>;
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def vvp_scatter : SDNode<"VEISD::VVP_SCATTER", SDTScatterVVP,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def vvp_gather : SDNode<"VEISD::VVP_GATHER", SDTGatherVVP,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def vvp_load : SDNode<"VEISD::VVP_LOAD", SDTLoadVVP,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand ]>;
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def vvp_store : SDNode<"VEISD::VVP_STORE", SDTStoreVVP,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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// Reductions
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// int reductions
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def vvp_reduce_add : SDNode<"VEISD::VVP_REDUCE_ADD", SDTReduceVVP>;
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def vvp_reduce_and : SDNode<"VEISD::VVP_REDUCE_AND", SDTReduceVVP>;
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def vvp_reduce_or : SDNode<"VEISD::VVP_REDUCE_OR", SDTReduceVVP>;
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def vvp_reduce_xor : SDNode<"VEISD::VVP_REDUCE_XOR", SDTReduceVVP>;
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def vvp_reduce_smax : SDNode<"VEISD::VVP_REDUCE_SMAX", SDTReduceVVP>;
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def vvp_select : SDNode<"VEISD::VVP_SELECT", SDTSelectVVP>;
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// setcc (lhs, rhs, cc, mask, vl)
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def vvp_setcc : SDNode<"VEISD::VVP_SETCC", SDTSetCCVVP>;
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