302 lines
9.4 KiB
C++
302 lines
9.4 KiB
C++
//===- X86CompressEVEX.cpp ------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass compresses instructions from EVEX space to legacy/VEX/EVEX space
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// when possible in order to reduce code size or facilitate HW decoding.
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//
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// Possible compression:
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// a. AVX512 instruction (EVEX) -> AVX instruction (VEX)
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// b. Promoted instruction (EVEX) -> pre-promotion instruction (legacy/VEX)
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// c. NDD (EVEX) -> non-NDD (legacy)
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// d. NF_ND (EVEX) -> NF (EVEX)
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//
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// Compression a, b and c can always reduce code size, with some exceptions
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// such as promoted 16-bit CRC32 which is as long as the legacy version.
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//
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// legacy:
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// crc32w %si, %eax ## encoding: [0x66,0xf2,0x0f,0x38,0xf1,0xc6]
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// promoted:
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// crc32w %si, %eax ## encoding: [0x62,0xf4,0x7d,0x08,0xf1,0xc6]
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//
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// From performance perspective, these should be same (same uops and same EXE
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// ports). From a FMV perspective, an older legacy encoding is preferred b/c it
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// can execute in more places (broader HW install base). So we will still do
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// the compression.
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//
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// Compression d can help hardware decode (HW may skip reading the NDD
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// register) although the instruction length remains unchanged.
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "MCTargetDesc/X86InstComments.h"
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Pass.h"
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#include <atomic>
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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// Including the generated EVEX compression tables.
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struct X86CompressEVEXTableEntry {
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uint16_t OldOpc;
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uint16_t NewOpc;
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bool operator<(const X86CompressEVEXTableEntry &RHS) const {
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return OldOpc < RHS.OldOpc;
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}
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friend bool operator<(const X86CompressEVEXTableEntry &TE, unsigned Opc) {
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return TE.OldOpc < Opc;
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}
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};
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#include "X86GenCompressEVEXTables.inc"
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#define COMP_EVEX_DESC "Compressing EVEX instrs when possible"
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#define COMP_EVEX_NAME "x86-compress-evex"
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#define DEBUG_TYPE COMP_EVEX_NAME
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namespace {
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class CompressEVEXPass : public MachineFunctionPass {
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public:
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static char ID;
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CompressEVEXPass() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return COMP_EVEX_DESC; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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// This pass runs after regalloc and doesn't support VReg operands.
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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};
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} // end anonymous namespace
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char CompressEVEXPass::ID = 0;
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static bool usesExtendedRegister(const MachineInstr &MI) {
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auto isHiRegIdx = [](unsigned Reg) {
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// Check for XMM register with indexes between 16 - 31.
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if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
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return true;
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// Check for YMM register with indexes between 16 - 31.
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if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
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return true;
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// Check for GPR with indexes between 16 - 31.
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if (X86II::isApxExtendedReg(Reg))
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return true;
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return false;
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};
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// Check that operands are not ZMM regs or
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// XMM/YMM regs with hi indexes between 16 - 31.
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for (const MachineOperand &MO : MI.explicit_operands()) {
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if (!MO.isReg())
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continue;
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Register Reg = MO.getReg();
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assert(!X86II::isZMMReg(Reg) &&
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"ZMM instructions should not be in the EVEX->VEX tables");
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if (isHiRegIdx(Reg))
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return true;
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}
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return false;
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}
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// Do any custom cleanup needed to finalize the conversion.
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static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) {
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(void)NewOpc;
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unsigned Opc = MI.getOpcode();
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switch (Opc) {
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case X86::VALIGNDZ128rri:
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case X86::VALIGNDZ128rmi:
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case X86::VALIGNQZ128rri:
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case X86::VALIGNQZ128rmi: {
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assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) &&
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"Unexpected new opcode!");
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unsigned Scale =
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(Opc == X86::VALIGNQZ128rri || Opc == X86::VALIGNQZ128rmi) ? 8 : 4;
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MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
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Imm.setImm(Imm.getImm() * Scale);
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break;
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}
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case X86::VSHUFF32X4Z256rmi:
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case X86::VSHUFF32X4Z256rri:
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case X86::VSHUFF64X2Z256rmi:
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case X86::VSHUFF64X2Z256rri:
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case X86::VSHUFI32X4Z256rmi:
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case X86::VSHUFI32X4Z256rri:
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case X86::VSHUFI64X2Z256rmi:
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case X86::VSHUFI64X2Z256rri: {
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assert((NewOpc == X86::VPERM2F128rr || NewOpc == X86::VPERM2I128rr ||
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NewOpc == X86::VPERM2F128rm || NewOpc == X86::VPERM2I128rm) &&
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"Unexpected new opcode!");
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MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
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int64_t ImmVal = Imm.getImm();
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// Set bit 5, move bit 1 to bit 4, copy bit 0.
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Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));
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break;
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}
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case X86::VRNDSCALEPDZ128rri:
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case X86::VRNDSCALEPDZ128rmi:
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case X86::VRNDSCALEPSZ128rri:
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case X86::VRNDSCALEPSZ128rmi:
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case X86::VRNDSCALEPDZ256rri:
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case X86::VRNDSCALEPDZ256rmi:
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case X86::VRNDSCALEPSZ256rri:
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case X86::VRNDSCALEPSZ256rmi:
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case X86::VRNDSCALESDZr:
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case X86::VRNDSCALESDZm:
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case X86::VRNDSCALESSZr:
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case X86::VRNDSCALESSZm:
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case X86::VRNDSCALESDZr_Int:
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case X86::VRNDSCALESDZm_Int:
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case X86::VRNDSCALESSZr_Int:
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case X86::VRNDSCALESSZm_Int:
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const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
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int64_t ImmVal = Imm.getImm();
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// Ensure that only bits 3:0 of the immediate are used.
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if ((ImmVal & 0xf) != ImmVal)
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return false;
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break;
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}
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return true;
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}
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static bool isRedundantNewDataDest(MachineInstr &MI, const X86Subtarget &ST) {
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// $rbx = ADD64rr_ND $rbx, $rax / $rbx = ADD64rr_ND $rax, $rbx
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// ->
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// $rbx = ADD64rr $rbx, $rax
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const MCInstrDesc &Desc = MI.getDesc();
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Register Reg0 = MI.getOperand(0).getReg();
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const MachineOperand &Op1 = MI.getOperand(1);
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if (!Op1.isReg())
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return false;
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Register Reg1 = Op1.getReg();
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if (Reg1 == Reg0)
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return true;
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// Op1 and Op2 may be commutable for ND instructions.
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if (!Desc.isCommutable() || Desc.getNumOperands() < 3 ||
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!MI.getOperand(2).isReg() || MI.getOperand(2).getReg() != Reg0)
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return false;
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// Opcode may change after commute, e.g. SHRD -> SHLD
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ST.getInstrInfo()->commuteInstruction(MI, false, 1, 2);
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return true;
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}
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static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
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uint64_t TSFlags = MI.getDesc().TSFlags;
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// Check for EVEX instructions only.
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if ((TSFlags & X86II::EncodingMask) != X86II::EVEX)
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return false;
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// Instructions with mask or 512-bit vector can't be converted to VEX.
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if (TSFlags & (X86II::EVEX_K | X86II::EVEX_L2))
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return false;
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// EVEX_B has several meanings.
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// AVX512:
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// register form: rounding control or SAE
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// memory form: broadcast
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//
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// APX:
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// MAP4: NDD
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//
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// For AVX512 cases, EVEX prefix is needed in order to carry this information
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// thus preventing the transformation to VEX encoding.
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bool IsND = X86II::hasNewDataDest(TSFlags);
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if (TSFlags & X86II::EVEX_B)
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if (!IsND || !isRedundantNewDataDest(MI, ST))
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return false;
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ArrayRef<X86CompressEVEXTableEntry> Table = ArrayRef(X86CompressEVEXTable);
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unsigned Opc = MI.getOpcode();
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const auto *I = llvm::lower_bound(Table, Opc);
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if (I == Table.end() || I->OldOpc != Opc) {
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assert(!IsND && "Missing entry for ND instruction");
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return false;
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}
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if (!IsND) {
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if (usesExtendedRegister(MI) || !checkPredicate(I->NewOpc, &ST) ||
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!performCustomAdjustments(MI, I->NewOpc))
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return false;
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}
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const MCInstrDesc &NewDesc = ST.getInstrInfo()->get(I->NewOpc);
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MI.setDesc(NewDesc);
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unsigned AsmComment;
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switch (NewDesc.TSFlags & X86II::EncodingMask) {
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case X86II::LEGACY:
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AsmComment = X86::AC_EVEX_2_LEGACY;
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break;
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case X86II::VEX:
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AsmComment = X86::AC_EVEX_2_VEX;
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break;
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case X86II::EVEX:
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AsmComment = X86::AC_EVEX_2_EVEX;
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assert(IsND && (NewDesc.TSFlags & X86II::EVEX_NF) &&
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"Unknown EVEX2EVEX compression");
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break;
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default:
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llvm_unreachable("Unknown EVEX compression");
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}
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MI.setAsmPrinterFlag(AsmComment);
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if (IsND)
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MI.tieOperands(0, 1);
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return true;
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}
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bool CompressEVEXPass::runOnMachineFunction(MachineFunction &MF) {
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#ifndef NDEBUG
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// Make sure the tables are sorted.
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static std::atomic<bool> TableChecked(false);
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if (!TableChecked.load(std::memory_order_relaxed)) {
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assert(llvm::is_sorted(X86CompressEVEXTable) &&
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"X86CompressEVEXTable is not sorted!");
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TableChecked.store(true, std::memory_order_relaxed);
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}
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#endif
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const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
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if (!ST.hasAVX512() && !ST.hasEGPR() && !ST.hasNDD())
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return false;
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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// Traverse the basic block.
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for (MachineInstr &MI : MBB)
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Changed |= CompressEVEXImpl(MI, ST);
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}
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return Changed;
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}
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INITIALIZE_PASS(CompressEVEXPass, COMP_EVEX_NAME, COMP_EVEX_DESC, false, false)
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FunctionPass *llvm::createX86CompressEVEXPass() {
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return new CompressEVEXPass();
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}
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