45 lines
2 KiB
TableGen
45 lines
2 KiB
TableGen
//===---- X86InstrRAOINT.td -------------------------------*- tablegen -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions that make up the Intel RAO-INT
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// instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RAO-INT instructions
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def SDTRAOBinaryArith : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
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def X86rao_add : SDNode<"X86ISD::AADD", SDTRAOBinaryArith,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def X86rao_or : SDNode<"X86ISD::AOR", SDTRAOBinaryArith,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def X86rao_xor : SDNode<"X86ISD::AXOR", SDTRAOBinaryArith,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def X86rao_and : SDNode<"X86ISD::AAND", SDTRAOBinaryArith,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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multiclass RAOINT_BASE<string OpcodeStr> {
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let Predicates = [HasRAOINT] in
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def 32mr : I<0xfc, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
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!strconcat("a", OpcodeStr, "{l}\t{$src, $dst|$dst, $src}"),
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[(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR32:$src)]>,
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Sched<[WriteALURMW]>;
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let Predicates = [HasRAOINT, In64BitMode] in
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def 64mr : I<0xfc, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
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!strconcat("a", OpcodeStr, "{q}\t{$src, $dst|$dst, $src}"),
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[(!cast<SDNode>("X86rao_" # OpcodeStr) addr:$dst, GR64:$src)]>,
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Sched<[WriteALURMW]>, REX_W;
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}
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defm AADD : RAOINT_BASE<"add">, T8;
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defm AAND : RAOINT_BASE<"and">, T8, PD;
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defm AOR : RAOINT_BASE<"or" >, T8, XD;
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defm AXOR : RAOINT_BASE<"xor">, T8, XS;
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