194 lines
8.1 KiB
TableGen
194 lines
8.1 KiB
TableGen
//====-- X86InstrTBM.td - TBM X86 Instruction Definition -*- tablegen -*-=====//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defining the TBM X86 instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// TBM Instructions
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//
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let Predicates = [HasTBM], Defs = [EFLAGS] in {
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multiclass tbm_bextri<bits<8> opc, RegisterClass RC, string OpcodeStr,
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X86MemOperand x86memop, PatFrag ld_frag,
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SDNode OpNode, Operand immtype,
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SDPatternOperator immoperator,
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X86FoldableSchedWrite Sched> {
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def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
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!strconcat(OpcodeStr,
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"\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
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[(set RC:$dst, (OpNode RC:$src1, immoperator:$cntl))]>,
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XOP, XOPA, Sched<[Sched]>;
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def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
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(ins x86memop:$src1, immtype:$cntl),
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!strconcat(OpcodeStr,
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"\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
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[(set RC:$dst, (OpNode (ld_frag addr:$src1), immoperator:$cntl))]>,
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XOP, XOPA, Sched<[Sched.Folded]>;
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}
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defm BEXTRI32 : tbm_bextri<0x10, GR32, "bextr{l}", i32mem, loadi32,
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X86bextri, i32imm, timm, WriteBEXTR>;
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let ImmT = Imm32S in
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defm BEXTRI64 : tbm_bextri<0x10, GR64, "bextr{q}", i64mem, loadi64,
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X86bextri, i64i32imm,
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i64timmSExt32, WriteBEXTR>, REX_W;
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multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
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RegisterClass RC, string OpcodeStr,
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X86MemOperand x86memop, X86FoldableSchedWrite Sched> {
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let hasSideEffects = 0 in {
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def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
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!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>,
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XOP, VVVV, XOP9, Sched<[Sched]>;
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let mayLoad = 1 in
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def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
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!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>,
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XOP, VVVV, XOP9, Sched<[Sched.Folded]>;
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}
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}
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multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
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X86FoldableSchedWrite Sched,
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Format FormReg, Format FormMem> {
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defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr#"{l}",
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i32mem, Sched>;
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defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr#"{q}",
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i64mem, Sched>, REX_W;
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}
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defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>;
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defm BLCI : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>;
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defm BLCIC : tbm_binary_intr<0x01, "blcic", WriteALU, MRM5r, MRM5m>;
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defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>;
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defm BLCS : tbm_binary_intr<0x01, "blcs", WriteALU, MRM3r, MRM3m>;
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defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>;
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defm BLSIC : tbm_binary_intr<0x01, "blsic", WriteALU, MRM6r, MRM6m>;
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defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", WriteALU, MRM7r, MRM7m>;
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defm TZMSK : tbm_binary_intr<0x01, "tzmsk", WriteALU, MRM4r, MRM4m>;
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} // HasTBM, EFLAGS
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// Use BEXTRI for 64-bit 'and' with large immediate 'mask'.
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let Predicates = [HasTBM] in {
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def : Pat<(and GR64:$src, AndMask64:$mask),
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(BEXTRI64ri GR64:$src, (BEXTRMaskXForm imm:$mask))>;
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def : Pat<(and (loadi64 addr:$src), AndMask64:$mask),
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(BEXTRI64mi addr:$src, (BEXTRMaskXForm imm:$mask))>;
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}
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//===----------------------------------------------------------------------===//
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// Pattern fragments to auto generate TBM instructions.
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//===----------------------------------------------------------------------===//
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let Predicates = [HasTBM] in {
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// FIXME: patterns for the load versions are not implemented
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def : Pat<(and GR32:$src, (add GR32:$src, 1)),
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(BLCFILL32rr GR32:$src)>;
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def : Pat<(and GR64:$src, (add GR64:$src, 1)),
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(BLCFILL64rr GR64:$src)>;
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def : Pat<(or GR32:$src, (not (add GR32:$src, 1))),
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(BLCI32rr GR32:$src)>;
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def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
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(BLCI64rr GR64:$src)>;
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// Extra patterns because opt can optimize the above patterns to this.
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def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
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(BLCI32rr GR32:$src)>;
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def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
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(BLCI64rr GR64:$src)>;
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def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
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(BLCIC32rr GR32:$src)>;
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def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),
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(BLCIC64rr GR64:$src)>;
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def : Pat<(xor GR32:$src, (add GR32:$src, 1)),
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(BLCMSK32rr GR32:$src)>;
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def : Pat<(xor GR64:$src, (add GR64:$src, 1)),
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(BLCMSK64rr GR64:$src)>;
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def : Pat<(or GR32:$src, (add GR32:$src, 1)),
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(BLCS32rr GR32:$src)>;
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def : Pat<(or GR64:$src, (add GR64:$src, 1)),
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(BLCS64rr GR64:$src)>;
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def : Pat<(or GR32:$src, (add GR32:$src, -1)),
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(BLSFILL32rr GR32:$src)>;
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def : Pat<(or GR64:$src, (add GR64:$src, -1)),
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(BLSFILL64rr GR64:$src)>;
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def : Pat<(or (not GR32:$src), (add GR32:$src, -1)),
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(BLSIC32rr GR32:$src)>;
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def : Pat<(or (not GR64:$src), (add GR64:$src, -1)),
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(BLSIC64rr GR64:$src)>;
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def : Pat<(or (not GR32:$src), (add GR32:$src, 1)),
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(T1MSKC32rr GR32:$src)>;
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def : Pat<(or (not GR64:$src), (add GR64:$src, 1)),
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(T1MSKC64rr GR64:$src)>;
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def : Pat<(and (not GR32:$src), (add GR32:$src, -1)),
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(TZMSK32rr GR32:$src)>;
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def : Pat<(and (not GR64:$src), (add GR64:$src, -1)),
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(TZMSK64rr GR64:$src)>;
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// Patterns to match flag producing ops.
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def : Pat<(and_flag_nocf GR32:$src, (add GR32:$src, 1)),
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(BLCFILL32rr GR32:$src)>;
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def : Pat<(and_flag_nocf GR64:$src, (add GR64:$src, 1)),
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(BLCFILL64rr GR64:$src)>;
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def : Pat<(or_flag_nocf GR32:$src, (not (add GR32:$src, 1))),
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(BLCI32rr GR32:$src)>;
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def : Pat<(or_flag_nocf GR64:$src, (not (add GR64:$src, 1))),
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(BLCI64rr GR64:$src)>;
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// Extra patterns because opt can optimize the above patterns to this.
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def : Pat<(or_flag_nocf GR32:$src, (sub -2, GR32:$src)),
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(BLCI32rr GR32:$src)>;
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def : Pat<(or_flag_nocf GR64:$src, (sub -2, GR64:$src)),
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(BLCI64rr GR64:$src)>;
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def : Pat<(and_flag_nocf (not GR32:$src), (add GR32:$src, 1)),
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(BLCIC32rr GR32:$src)>;
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def : Pat<(and_flag_nocf (not GR64:$src), (add GR64:$src, 1)),
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(BLCIC64rr GR64:$src)>;
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def : Pat<(xor_flag_nocf GR32:$src, (add GR32:$src, 1)),
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(BLCMSK32rr GR32:$src)>;
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def : Pat<(xor_flag_nocf GR64:$src, (add GR64:$src, 1)),
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(BLCMSK64rr GR64:$src)>;
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def : Pat<(or_flag_nocf GR32:$src, (add GR32:$src, 1)),
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(BLCS32rr GR32:$src)>;
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def : Pat<(or_flag_nocf GR64:$src, (add GR64:$src, 1)),
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(BLCS64rr GR64:$src)>;
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def : Pat<(or_flag_nocf GR32:$src, (add GR32:$src, -1)),
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(BLSFILL32rr GR32:$src)>;
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def : Pat<(or_flag_nocf GR64:$src, (add GR64:$src, -1)),
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(BLSFILL64rr GR64:$src)>;
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def : Pat<(or_flag_nocf (not GR32:$src), (add GR32:$src, -1)),
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(BLSIC32rr GR32:$src)>;
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def : Pat<(or_flag_nocf (not GR64:$src), (add GR64:$src, -1)),
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(BLSIC64rr GR64:$src)>;
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def : Pat<(or_flag_nocf (not GR32:$src), (add GR32:$src, 1)),
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(T1MSKC32rr GR32:$src)>;
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def : Pat<(or_flag_nocf (not GR64:$src), (add GR64:$src, 1)),
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(T1MSKC64rr GR64:$src)>;
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def : Pat<(and_flag_nocf (not GR32:$src), (add GR32:$src, -1)),
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(TZMSK32rr GR32:$src)>;
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def : Pat<(and_flag_nocf (not GR64:$src), (add GR64:$src, -1)),
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(TZMSK64rr GR64:$src)>;
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} // HasTBM
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