281 lines
11 KiB
C++
281 lines
11 KiB
C++
//===-- XtensaDisassembler.cpp - Disassembler for Xtensa ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the XtensaDisassembler class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/XtensaMCTargetDesc.h"
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#include "TargetInfo/XtensaTargetInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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#define DEBUG_TYPE "Xtensa-disassembler"
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using DecodeStatus = MCDisassembler::DecodeStatus;
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namespace {
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class XtensaDisassembler : public MCDisassembler {
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bool IsLittleEndian;
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public:
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XtensaDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool isLE)
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: MCDisassembler(STI, Ctx), IsLittleEndian(isLE) {}
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bool hasDensity() const {
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return STI.hasFeature(Xtensa::FeatureDensity);
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}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static MCDisassembler *createXtensaDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new XtensaDisassembler(STI, Ctx, true);
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaDisassembler() {
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TargetRegistry::RegisterMCDisassembler(getTheXtensaTarget(),
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createXtensaDisassembler);
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}
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static const unsigned ARDecoderTable[] = {
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Xtensa::A0, Xtensa::SP, Xtensa::A2, Xtensa::A3, Xtensa::A4, Xtensa::A5,
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Xtensa::A6, Xtensa::A7, Xtensa::A8, Xtensa::A9, Xtensa::A10, Xtensa::A11,
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Xtensa::A12, Xtensa::A13, Xtensa::A14, Xtensa::A15};
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static DecodeStatus DecodeARRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= std::size(ARDecoderTable))
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return MCDisassembler::Fail;
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unsigned Reg = ARDecoderTable[RegNo];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static const unsigned SRDecoderTable[] = {Xtensa::SAR, 3};
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static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo > 255)
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return MCDisassembler::Fail;
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for (unsigned i = 0; i < std::size(SRDecoderTable); i += 2) {
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if (SRDecoderTable[i + 1] == RegNo) {
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unsigned Reg = SRDecoderTable[i];
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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}
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return MCDisassembler::Fail;
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}
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static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
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uint64_t Address, uint64_t Offset,
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uint64_t InstSize, MCInst &MI,
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const void *Decoder) {
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const MCDisassembler *Dis = static_cast<const MCDisassembler *>(Decoder);
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return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch, Offset, /*OpSize=*/0,
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InstSize);
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}
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static DecodeStatus decodeCallOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<18>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Imm << 2)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeJumpOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<18>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(SignExtend64<18>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeBranchOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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switch (Inst.getOpcode()) {
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case Xtensa::BEQZ:
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case Xtensa::BGEZ:
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case Xtensa::BLTZ:
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case Xtensa::BNEZ:
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assert(isUInt<12>(Imm) && "Invalid immediate");
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if (!tryAddingSymbolicOperand(SignExtend64<12>(Imm) + 4 + Address, true,
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Address, 0, 3, Inst, Decoder))
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Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm)));
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break;
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default:
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assert(isUInt<8>(Imm) && "Invalid immediate");
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if (!tryAddingSymbolicOperand(SignExtend64<8>(Imm) + 4 + Address, true,
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Address, 0, 3, Inst, Decoder))
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Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm)));
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}
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeL32ROperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<16>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(
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SignExtend64<17>((Imm << 2) + 0x40000 + (Address & 0x3))));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm8Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<8>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm8_sh8Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<8>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 8)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm12Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<12>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(SignExtend64<12>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeUimm4Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<4>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeUimm5Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<5>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImm1_16Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<4>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm + 1));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<5>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(32 - Imm));
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return MCDisassembler::Success;
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}
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static int64_t TableB4const[16] = {-1, 1, 2, 3, 4, 5, 6, 7,
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8, 10, 12, 16, 32, 64, 128, 256};
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static DecodeStatus decodeB4constOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<4>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(TableB4const[Imm]));
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return MCDisassembler::Success;
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}
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static int64_t TableB4constu[16] = {32768, 65536, 2, 3, 4, 5, 6, 7,
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8, 10, 12, 16, 32, 64, 128, 256};
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static DecodeStatus decodeB4constuOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder) {
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assert(isUInt<4>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(TableB4constu[Imm]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMem8Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<12>(Imm) && "Invalid immediate");
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DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
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Inst.addOperand(MCOperand::createImm((Imm >> 4) & 0xff));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMem16Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<12>(Imm) && "Invalid immediate");
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DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
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Inst.addOperand(MCOperand::createImm((Imm >> 3) & 0x1fe));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMem32Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<12>(Imm) && "Invalid immediate");
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DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
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Inst.addOperand(MCOperand::createImm((Imm >> 2) & 0x3fc));
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return MCDisassembler::Success;
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}
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/// Read three bytes from the ArrayRef and return 24 bit data
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static DecodeStatus readInstruction24(ArrayRef<uint8_t> Bytes, uint64_t Address,
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uint64_t &Size, uint32_t &Insn,
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bool IsLittleEndian) {
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// We want to read exactly 3 Bytes of data.
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if (Bytes.size() < 3) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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if (!IsLittleEndian) {
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report_fatal_error("Big-endian mode currently is not supported!");
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} else {
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Insn = (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
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}
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Size = 3;
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return MCDisassembler::Success;
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}
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#include "XtensaGenDisassemblerTables.inc"
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DecodeStatus XtensaDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &CS) const {
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uint32_t Insn;
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DecodeStatus Result;
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Result = readInstruction24(Bytes, Address, Size, Insn, IsLittleEndian);
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if (Result == MCDisassembler::Fail)
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return MCDisassembler::Fail;
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LLVM_DEBUG(dbgs() << "Trying Xtensa 24-bit instruction table :\n");
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Result = decodeInstruction(DecoderTable24, MI, Insn, Address, this, STI);
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return Result;
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}
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