69 lines
2.9 KiB
C++
69 lines
2.9 KiB
C++
//===- XtensaTargetMachine.cpp - Define TargetMachine for Xtensa ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Implements the info about Xtensa target spec.
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//
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//===----------------------------------------------------------------------===//
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#include "XtensaTargetMachine.h"
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#include "TargetInfo/XtensaTargetInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include <optional>
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using namespace llvm;
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTarget() {
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// Register the target.
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RegisterTargetMachine<XtensaTargetMachine> A(getTheXtensaTarget());
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}
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static std::string computeDataLayout(const Triple &TT, StringRef CPU,
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const TargetOptions &Options,
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bool IsLittle) {
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std::string Ret = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32";
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return Ret;
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}
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static Reloc::Model getEffectiveRelocModel(bool JIT,
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std::optional<Reloc::Model> RM) {
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if (!RM || JIT)
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return Reloc::Static;
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return *RM;
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}
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XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM,
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CodeGenOptLevel OL, bool JIT,
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bool IsLittle)
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: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, IsLittle), TT,
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CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
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getEffectiveCodeModel(CM, CodeModel::Small), OL),
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TLOF(std::make_unique<TargetLoweringObjectFileELF>()) {
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initAsmInfo();
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}
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XtensaTargetMachine::XtensaTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM,
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CodeGenOptLevel OL, bool JIT)
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: XtensaTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
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TargetPassConfig *XtensaTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new TargetPassConfig(*this, PM);
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}
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