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bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AArch64/GlobalISel/combine-fshr.mir
Sam Vervaeck 174b6f4d4e
Embed LLVM 18.1.8
2025-02-14 19:21:04 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=arm64-unknown-unknown -global-isel -run-pass=aarch64-prelegalizer-combiner %s -o - | FileCheck %s
---
name: fshr_i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: fshr_i8
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s8) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s8)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s8)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%3:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %3(s32)
%4:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %4(s32)
%5:_(s32) = COPY $w2
%2:_(s8) = G_TRUNC %5(s32)
%6:_(s8) = G_FSHR %0, %1, %2(s8)
%7:_(s32) = G_ANYEXT %6(s8)
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i16
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: fshr_i16
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s16)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%3:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %3(s32)
%4:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %4(s32)
%5:_(s32) = COPY $w2
%2:_(s16) = G_TRUNC %5(s32)
%6:_(s16) = G_FSHR %0, %1, %2(s16)
%7:_(s32) = G_ANYEXT %6(s16)
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i32
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: fshr_i32
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = COPY $w2
%3:_(s32) = G_FSHR %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i64
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: fshr_i64
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s64)
; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s64) = G_FSHR %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
---
name: fshr_i8_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i8_const_shift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 5
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s8) = G_FSHR [[TRUNC]], [[TRUNC1]], [[C]](s8)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s8)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_CONSTANT i8 5
%5:_(s8) = G_FSHR %0, %1, %4(s8)
%6:_(s32) = G_ANYEXT %5(s8)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i8_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i8_const_overshift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s8) = G_FSHR [[TRUNC]], [[TRUNC1]], [[C]](s8)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s8)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_CONSTANT i8 10
%5:_(s8) = G_FSHR %0, %1, %4(s8)
%6:_(s32) = G_ANYEXT %5(s8)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i8_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i8_shift_by_bidwidth
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_CONSTANT i8 8
%5:_(s8) = G_FSHR %0, %1, %4(s8)
%6:_(s32) = G_ANYEXT %5(s8)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i16_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i16_const_shift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 5
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[TRUNC]], [[TRUNC1]], [[C]](s16)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_CONSTANT i16 5
%5:_(s16) = G_FSHR %0, %1, %4(s16)
%6:_(s32) = G_ANYEXT %5(s16)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i16_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i16_const_overshift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[TRUNC]], [[TRUNC1]], [[C]](s16)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_CONSTANT i16 20
%5:_(s16) = G_FSHR %0, %1, %4(s16)
%6:_(s32) = G_ANYEXT %5(s16)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i16_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i16_shift_by_bidwidth
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_CONSTANT i16 16
%5:_(s16) = G_FSHR %0, %1, %4(s16)
%6:_(s32) = G_ANYEXT %5(s16)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i32_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i32_const_shift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s32)
; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_CONSTANT i32 5
%3:_(s32) = G_FSHR %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i32_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i32_const_overshift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s32)
; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_CONSTANT i32 42
%3:_(s32) = G_FSHR %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i32_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i32_shift_by_bidwidth
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_CONSTANT i32 32
%3:_(s32) = G_FSHR %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i64_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: fshr_i64_const_shift
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_CONSTANT i64 5
%3:_(s64) = G_FSHR %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
---
name: fshr_i64_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: fshr_i64_const_overshift
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_CONSTANT i64 72
%3:_(s64) = G_FSHR %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
---
name: fshr_i64_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: fshr_i64_shift_by_bidwidth
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_CONSTANT i64 64
%3:_(s64) = G_FSHR %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
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