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bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AArch64/GlobalISel/combine-icmp-of-binop-to-icmp-of-0.mir
Sam Vervaeck 174b6f4d4e
Embed LLVM 18.1.8
2025-02-14 19:21:04 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
# Test:
# (X + Y) == X --> Y == 0
# (X - Y) == X --> Y == 0
# (X ^ Y) == X --> Y == 0
# (X + Y) != X --> Y != 0
# (X - Y) != X --> Y != 0
# (X ^ Y) != X --> Y != 0
#
# And all commuted cases.
...
---
name: add_scalar_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_eq
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_eq
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: add_scalar_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_eq_commuted_in_op
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %y, %x
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_eq_commuted_in_op
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %y, %x
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: add_scalar_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_eq_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_eq_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_eq
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_eq
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_eq_commuted_in_op
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %y, %x
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_eq_commuted_in_op
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %y, %x
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_eq_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_eq_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: sub_scalar_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: sub_scalar_eq
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_SUB %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sub_vector_eq
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: sub_vector_eq
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_SUB %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: sub_scalar_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: sub_scalar_eq_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_SUB %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sub_vector_eq_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: sub_vector_eq_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_SUB %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: add_scalar_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_ne
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_ne
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: add_scalar_ne_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_ne_commuted_in_op
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %y, %x
%cmp:_(s1) = G_ICMP intpred(ne), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_ne_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_ne_commuted_in_op
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %y, %x
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: add_scalar_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: add_scalar_ne_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: add_vector_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: add_vector_ne_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_ADD %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_ne
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_ne
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_ne_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_ne_commuted_in_op
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %y, %x
%cmp:_(s1) = G_ICMP intpred(ne), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_ne_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_ne_commuted_in_op
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %y, %x
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: xor_scalar_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: xor_scalar_ne_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_XOR %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: xor_vector_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: xor_vector_ne_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_XOR %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: sub_scalar_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: sub_scalar_ne
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_SUB %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sub_vector_ne
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: sub_vector_ne
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_SUB %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: sub_scalar_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: sub_scalar_ne_commuted_in_cmp
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(ne), %y(s32), [[C]]
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_SUB %x, %y
%cmp:_(s1) = G_ICMP intpred(ne), %x(s32), %op
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: sub_vector_ne_commuted_in_cmp
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: sub_vector_ne_commuted_in_cmp
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(ne), %y(<4 x s32>), [[BUILD_VECTOR]]
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_SUB %x, %y
%cmp:_(<4 x s1>) = G_ICMP intpred(ne), %x(<4 x s32>), %op
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: dont_combine_sub_scalar_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: dont_combine_sub_scalar_eq_commuted_in_op
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: %op:_(s32) = G_SUB %y, %x
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_SUB %y, %x
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: dont_combine_sub_vector_eq_commuted_in_op
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: dont_combine_sub_vector_eq_commuted_in_op
; CHECK: liveins: $q0, $q1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: %y:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: %op:_(<4 x s32>) = G_SUB %y, %x
; CHECK-NEXT: %cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
; CHECK-NEXT: %ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
; CHECK-NEXT: $d0 = COPY %ext(<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
%x:_(<4 x s32>) = COPY $q0
%y:_(<4 x s32>) = COPY $q1
%op:_(<4 x s32>) = G_SUB %y, %x
%cmp:_(<4 x s1>) = G_ICMP intpred(eq), %op(<4 x s32>), %x
%ext:_(<4 x s16>) = G_ANYEXT %cmp(<4 x s1>)
$d0 = COPY %ext(<4 x s16>)
RET_ReallyLR implicit $d0
...
---
name: dont_combine_not_equality
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: dont_combine_not_equality
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: %op:_(s32) = G_ADD %x, %y
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(slt), %op(s32), %x
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(slt), %op(s32), %x
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
...
---
name: dont_combine_unique_operands
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: dont_combine_unique_operands
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:_(s32) = COPY $w0
; CHECK-NEXT: %y:_(s32) = COPY $w1
; CHECK-NEXT: %z:_(s32) = COPY $w2
; CHECK-NEXT: %op:_(s32) = G_ADD %x, %y
; CHECK-NEXT: %cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %z
; CHECK-NEXT: %ext:_(s32) = G_ZEXT %cmp(s1)
; CHECK-NEXT: $w0 = COPY %ext(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%x:_(s32) = COPY $w0
%y:_(s32) = COPY $w1
%z:_(s32) = COPY $w2
%op:_(s32) = G_ADD %x, %y
%cmp:_(s1) = G_ICMP intpred(eq), %op(s32), %z
%ext:_(s32) = G_ZEXT %cmp(s1)
$w0 = COPY %ext(s32)
RET_ReallyLR implicit $w0
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