132 lines
3.7 KiB
YAML
132 lines
3.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: shl_by_ge_bw
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: shl_by_ge_bw
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[DEF]](s16)
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; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%1:_(s32) = COPY $w0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s16) = G_CONSTANT i16 20
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%3:_(s16) = G_SHL %0, %2(s16)
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%4:_(s32) = G_ANYEXT %3(s16)
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: lshr_by_ge_bw
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: lshr_by_ge_bw
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[DEF]](s16)
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; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%1:_(s32) = COPY $w0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s16) = G_CONSTANT i16 16
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%3:_(s16) = G_LSHR %0, %2(s16)
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%4:_(s32) = G_ANYEXT %3(s16)
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: ashr_by_ge_bw
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$w0' }
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body: |
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bb.1:
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liveins: $w0
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; CHECK-LABEL: name: ashr_by_ge_bw
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; CHECK: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[DEF]](s16)
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; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%1:_(s32) = COPY $w0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s16) = G_CONSTANT i16 20
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%3:_(s16) = G_ASHR %0, %2(s16)
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%4:_(s32) = G_ANYEXT %3(s16)
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$w0 = COPY %4(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: shl_by_ge_bw_vector
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0' }
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body: |
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: shl_by_ge_bw_vector
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %shl:_(<4 x s32>) = G_IMPLICIT_DEF
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; CHECK-NEXT: $q0 = COPY %shl(<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%1:_(<4 x s32>) = COPY $q0
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%0:_(s32) = G_CONSTANT i32 32
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%bv:_(<4 x s32>) = G_BUILD_VECTOR %0, %0, %0, %0
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%shl:_(<4 x s32>) = G_SHL %1, %bv(<4 x s32>)
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$q0 = COPY %shl(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: shl_by_ge_bw_vector_partial
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0' }
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body: |
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: shl_by_ge_bw_vector_partial
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
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; CHECK-NEXT: %small:_(s32) = G_CONSTANT i32 4
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; CHECK-NEXT: %bv:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), %small(s32)
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; CHECK-NEXT: %shl:_(<4 x s32>) = G_SHL [[COPY]], %bv(<4 x s32>)
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; CHECK-NEXT: $q0 = COPY %shl(<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%1:_(<4 x s32>) = COPY $q0
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%0:_(s32) = G_CONSTANT i32 32
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%small:_(s32) = G_CONSTANT i32 4
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%bv:_(<4 x s32>) = G_BUILD_VECTOR %0, %0, %0, %small
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%shl:_(<4 x s32>) = G_SHL %1, %bv(<4 x s32>)
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$q0 = COPY %shl(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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