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bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-dead-cc-defs-in-fcmp.mir
Sam Vervaeck 174b6f4d4e
Embed LLVM 18.1.8
2025-02-14 19:21:04 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=aarch64-post-select-optimize -verify-machineinstrs %s -o - | FileCheck %s
---
name: test_fcmp_dead_cc
alignment: 4
legalized: true
regBankSelected: true
selected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$w1' }
body: |
bb.1:
liveins: $w1, $x0, $s0, $s1
; CHECK-LABEL: name: test_fcmp_dead_cc
; CHECK: liveins: $w1, $x0, $s0, $s1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr
; CHECK-NEXT: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
; CHECK-NEXT: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 31
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSELWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr64 = COPY $x0
%2:gpr32 = COPY $w1
%3:fpr32 = COPY $s0
%4:fpr32 = COPY $s1
%26:gpr32 = COPY $wzr
FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr
%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr
%14:gpr32common = UBFMWri %12, 1, 31
%60:gpr32 = MOVi32imm 1
%16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
$w0 = COPY %16
RET_ReallyLR implicit $w0
...
---
name: test_fcmp_64_dead_cc
alignment: 4
legalized: true
regBankSelected: true
selected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$w1' }
body: |
bb.1:
liveins: $w1, $x0, $d0, $d1
; CHECK-LABEL: name: test_fcmp_64_dead_cc
; CHECK: liveins: $w1, $x0, $d0, $d1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY $d1
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: FCMPDrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr
; CHECK-NEXT: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
; CHECK-NEXT: FCMPDrr [[COPY2]], [[COPY3]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr]], 1, 31
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSELWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr64 = COPY $x0
%2:gpr32 = COPY $w1
%3:fpr64 = COPY $d0
%4:fpr64 = COPY $d1
%26:gpr32 = COPY $wzr
FCMPDrr %3, %4, implicit-def $nzcv, implicit $fpcr
%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
FCMPDrr %3, %4, implicit-def $nzcv, implicit $fpcr
%14:gpr32common = UBFMWri %12, 1, 31
%60:gpr32 = MOVi32imm 1
%16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
$w0 = COPY %16
RET_ReallyLR implicit $w0
...
---
name: test_fcmp_dead_cc_3_fcmps
alignment: 4
legalized: true
regBankSelected: true
selected: true
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$w1' }
body: |
bb.1:
liveins: $w1, $x0, $s0, $s1
; CHECK-LABEL: name: test_fcmp_dead_cc_3_fcmps
; CHECK: liveins: $w1, $x0, $s0, $s1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $s1
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr
; CHECK-NEXT: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
; CHECK-NEXT: FCMPSrr [[COPY2]], [[COPY3]], implicit-def dead $nzcv, implicit $fpcr
; CHECK-NEXT: [[SUBWrr1:%[0-9]+]]:gpr32 = SUBWrr [[COPY1]], [[COPY4]]
; CHECK-NEXT: FCMPSrr [[COPY2]], [[COPY3]], implicit-def $nzcv, implicit $fpcr
; CHECK-NEXT: [[UBFMWri:%[0-9]+]]:gpr32common = UBFMWri [[SUBWrr1]], 1, 31
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[UBFMWri]], [[MOVi32imm]], 8, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSELWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr64 = COPY $x0
%2:gpr32 = COPY $w1
%3:fpr32 = COPY $s0
%4:fpr32 = COPY $s1
%26:gpr32 = COPY $wzr
FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr
%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr
%12:gpr32 = SUBSWrr %2, %26, implicit-def $nzcv
FCMPSrr %3, %4, implicit-def $nzcv, implicit $fpcr
%14:gpr32common = UBFMWri %12, 1, 31
%60:gpr32 = MOVi32imm 1
%16:gpr32 = CSELWr %14, %60, 8, implicit $nzcv
$w0 = COPY %16
RET_ReallyLR implicit $w0
...
---
name: test_impdef_subsx
alignment: 4
legalized: true
regBankSelected: true
selected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1
; CHECK-LABEL: name: test_impdef_subsx
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[SUBXrr:%[0-9]+]]:gpr64 = SUBXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[SUBXrr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%1:gpr64 = COPY $x0
%2:gpr64 = COPY $x1
%4:gpr64 = SUBSXrr %1, %2, implicit-def $nzcv
$x0 = COPY %4
RET_ReallyLR implicit $x0
...
---
name: test_impdef_subsw
alignment: 4
legalized: true
regBankSelected: true
selected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $w0, $w1
; CHECK-LABEL: name: test_impdef_subsw
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $x1
; CHECK-NEXT: [[SUBWrr:%[0-9]+]]:gpr32 = SUBWrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[SUBWrr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr32 = COPY $x0
%2:gpr32 = COPY $x1
%4:gpr32 = SUBSWrr %1, %2, implicit-def $nzcv
$w0 = COPY %4
RET_ReallyLR implicit $w0
...
---
name: test_impdef_addsx
alignment: 4
legalized: true
regBankSelected: true
selected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1
; CHECK-LABEL: name: test_impdef_addsx
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $x0 = COPY [[ADDXrr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%1:gpr64 = COPY $x0
%2:gpr64 = COPY $x1
%4:gpr64 = ADDSXrr %1, %2, implicit-def $nzcv
$x0 = COPY %4
RET_ReallyLR implicit $x0
...
---
name: test_impdef_addsw
alignment: 4
legalized: true
regBankSelected: true
selected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $w0, $w1
; CHECK-LABEL: name: test_impdef_addsw
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $x1
; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
; CHECK-NEXT: $w0 = COPY [[ADDWrr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr32 = COPY $x0
%2:gpr32 = COPY $x1
%4:gpr32 = ADDSWrr %1, %2, implicit-def $nzcv
$w0 = COPY %4
RET_ReallyLR implicit $w0
...
---
name: test_impdef_adcsx
alignment: 4
legalized: true
regBankSelected: true
selected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_impdef_adcsx
; CHECK: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
; CHECK-NEXT: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
; CHECK-NEXT: [[ADCXr:%[0-9]+]]:gpr64 = ADCXr [[COPY1]], [[COPY3]], implicit $nzcv
; CHECK-NEXT: $x0 = COPY [[ADDSXrr]]
; CHECK-NEXT: $x1 = COPY [[ADCXr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%1:gpr64 = COPY $x0
%2:gpr64 = COPY $x1
%3:gpr64 = COPY $x2
%4:gpr64 = COPY $x3
%5:gpr64 = ADDSXrr %1, %3, implicit-def $nzcv
%6:gpr64 = ADCSXr %2, %4, implicit-def $nzcv, implicit $nzcv
$x0 = COPY %5
$x1 = COPY %6
RET_ReallyLR implicit $x0, implicit $x1
...
---
name: test_impdef_adcsw
alignment: 4
legalized: true
regBankSelected: true
selected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $w0, $w1, $w2, $w3
; CHECK-LABEL: name: test_impdef_adcsw
; CHECK: liveins: $w0, $w1, $w2, $w3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
; CHECK-NEXT: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY2]], implicit-def $nzcv
; CHECK-NEXT: [[ADCWr:%[0-9]+]]:gpr32 = ADCWr [[COPY1]], [[COPY3]], implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[ADDSWrr]]
; CHECK-NEXT: $w1 = COPY [[ADCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
%1:gpr32 = COPY $w0
%2:gpr32 = COPY $w1
%3:gpr32 = COPY $w2
%4:gpr32 = COPY $w3
%5:gpr32 = ADDSWrr %1, %3, implicit-def $nzcv
%6:gpr32 = ADCSWr %2, %4, implicit-def $nzcv, implicit $nzcv
$w0 = COPY %5
$w1 = COPY %6
RET_ReallyLR implicit $w0, implicit $w1
...
---
name: test_impdef_sbcsx
alignment: 4
legalized: true
regBankSelected: true
selected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_impdef_sbcsx
; CHECK: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY $x3
; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY2]], implicit-def $nzcv
; CHECK-NEXT: [[SBCXr:%[0-9]+]]:gpr64 = SBCXr [[COPY1]], [[COPY3]], implicit $nzcv
; CHECK-NEXT: $x0 = COPY [[SUBSXrr]]
; CHECK-NEXT: $x1 = COPY [[SBCXr]]
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%1:gpr64 = COPY $x0
%2:gpr64 = COPY $x1
%3:gpr64 = COPY $x2
%4:gpr64 = COPY $x3
%5:gpr64 = SUBSXrr %1, %3, implicit-def $nzcv
%6:gpr64 = SBCSXr %2, %4, implicit-def $nzcv, implicit $nzcv
$x0 = COPY %5
$x1 = COPY %6
RET_ReallyLR implicit $x0, implicit $x1
...
---
name: test_impdef_sbcsw
alignment: 4
legalized: true
regBankSelected: true
selected: true
tracksRegLiveness: true
body: |
bb.1:
liveins: $w0, $w1, $w2, $w3
; CHECK-LABEL: name: test_impdef_sbcsw
; CHECK: liveins: $w0, $w1, $w2, $w3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $w3
; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY2]], implicit-def $nzcv
; CHECK-NEXT: [[SBCWr:%[0-9]+]]:gpr32 = SBCWr [[COPY1]], [[COPY3]], implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[SUBSWrr]]
; CHECK-NEXT: $w1 = COPY [[SBCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0, implicit $w1
%1:gpr32 = COPY $w0
%2:gpr32 = COPY $w1
%3:gpr32 = COPY $w2
%4:gpr32 = COPY $w3
%5:gpr32 = SUBSWrr %1, %3, implicit-def $nzcv
%6:gpr32 = SBCSWr %2, %4, implicit-def $nzcv, implicit $nzcv
$w0 = COPY %5
$w1 = COPY %6
RET_ReallyLR implicit $w0, implicit $w1
...
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