136 lines
5.1 KiB
YAML
136 lines
5.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="mulo_by_0" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
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# REQUIRES: asserts
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# (G_*MULO x, 0) -> 0 + no carry out
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...
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---
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name: umulo_zero
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: umulo_zero
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: %mulo:_(s32) = COPY %zero(s32)
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; CHECK-NEXT: %carry:_(s1) = G_CONSTANT i1 false
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; CHECK-NEXT: %carry_wide:_(s32) = G_ZEXT %carry(s1)
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; CHECK-NEXT: $w0 = COPY %mulo(s32)
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; CHECK-NEXT: $w1 = COPY %carry_wide(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%lhs:_(s32) = COPY $w0
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%zero:_(s32) = G_CONSTANT i32 0
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%mulo:_(s32), %carry:_(s1) = G_UMULO %lhs, %zero
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%carry_wide:_(s32) = G_ZEXT %carry(s1)
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$w0 = COPY %mulo(s32)
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$w1 = COPY %carry_wide
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RET_ReallyLR implicit $w0
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...
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---
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name: smulo_zero
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: smulo_zero
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: %mulo:_(s32) = COPY %zero(s32)
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; CHECK-NEXT: %carry:_(s1) = G_CONSTANT i1 false
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; CHECK-NEXT: %carry_wide:_(s32) = G_ZEXT %carry(s1)
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; CHECK-NEXT: $w0 = COPY %mulo(s32)
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; CHECK-NEXT: $w1 = COPY %carry_wide(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%lhs:_(s32) = COPY $w0
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%zero:_(s32) = G_CONSTANT i32 0
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%mulo:_(s32), %carry:_(s1) = G_SMULO %lhs, %zero
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%carry_wide:_(s32) = G_ZEXT %carry(s1)
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$w0 = COPY %mulo(s32)
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$w1 = COPY %carry_wide
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RET_ReallyLR implicit $w0
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...
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---
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name: wrong_cst
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; CHECK-LABEL: name: wrong_cst
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; CHECK: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %lhs:_(s32) = COPY $w0
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; CHECK-NEXT: %not_zero:_(s32) = G_CONSTANT i32 3
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; CHECK-NEXT: %mulo:_(s32), %carry:_(s1) = G_UMULO %lhs, %not_zero
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; CHECK-NEXT: %carry_wide:_(s32) = G_ZEXT %carry(s1)
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; CHECK-NEXT: $w0 = COPY %mulo(s32)
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; CHECK-NEXT: $w1 = COPY %carry_wide(s32)
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%lhs:_(s32) = COPY $w0
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%not_zero:_(s32) = G_CONSTANT i32 3
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%mulo:_(s32), %carry:_(s1) = G_UMULO %lhs, %not_zero
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%carry_wide:_(s32) = G_ZEXT %carry(s1)
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$w0 = COPY %mulo(s32)
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$w1 = COPY %carry_wide
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RET_ReallyLR implicit $w0
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...
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---
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name: umulo_vec_zero
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $x0
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; CHECK-LABEL: name: umulo_vec_zero
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; CHECK: liveins: $q0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
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; CHECK-NEXT: %mulo:_(<2 x s64>) = COPY %zero_vec(<2 x s64>)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
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; CHECK-NEXT: %carry:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1)
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; CHECK-NEXT: %carry_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %carry(<2 x s1>), %zero(s64)
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; CHECK-NEXT: %carry_wide:_(s64) = G_ZEXT %carry_elt_0(s1)
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; CHECK-NEXT: $q0 = COPY %mulo(<2 x s64>)
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; CHECK-NEXT: $x0 = COPY %carry_wide(s64)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%lhs:_(<2 x s64>) = COPY $q0
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%zero:_(s64) = G_CONSTANT i64 0
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%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
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%mulo:_(<2 x s64>), %carry:_(<2 x s1>) = G_UMULO %lhs, %zero_vec
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%carry_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %carry:_(<2 x s1>), %zero:_(s64)
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%carry_wide:_(s64) = G_ZEXT %carry_elt_0
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$q0 = COPY %mulo(<2 x s64>)
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$x0 = COPY %carry_wide
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RET_ReallyLR implicit $q0
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...
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---
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name: smulo_vec_zero
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $x0
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; CHECK-LABEL: name: smulo_vec_zero
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; CHECK: liveins: $q0, $x0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
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; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
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; CHECK-NEXT: %mulo:_(<2 x s64>) = COPY %zero_vec(<2 x s64>)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
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; CHECK-NEXT: %carry:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1)
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; CHECK-NEXT: %carry_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %carry(<2 x s1>), %zero(s64)
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; CHECK-NEXT: %carry_wide:_(s64) = G_ZEXT %carry_elt_0(s1)
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; CHECK-NEXT: $q0 = COPY %mulo(<2 x s64>)
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; CHECK-NEXT: $x0 = COPY %carry_wide(s64)
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; CHECK-NEXT: RET_ReallyLR implicit $q0
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%lhs:_(<2 x s64>) = COPY $q0
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%zero:_(s64) = G_CONSTANT i64 0
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%zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
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%mulo:_(<2 x s64>), %carry:_(<2 x s1>) = G_SMULO %lhs, %zero_vec
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%carry_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %carry:_(<2 x s1>), %zero:_(s64)
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%carry_wide:_(s64) = G_ZEXT %carry_elt_0
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$q0 = COPY %mulo(<2 x s64>)
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$x0 = COPY %carry_wide
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RET_ReallyLR implicit $q0
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