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bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
Sam Vervaeck 174b6f4d4e
Embed LLVM 18.1.8
2025-02-14 19:21:04 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple aarch64--- -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s
---
name: test_loop_phi_fpr_to_gpr
alignment: 4
legalized: true
regBankSelected: true
selected: false
failedISel: false
tracksRegLiveness: true
liveins: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test_loop_phi_fpr_to_gpr
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32 = PHI [[CSELWr]], %bb.1, %8, %bb.2
; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]]
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[FCVTHSr]], %subreg.hsub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: STRHHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `ptr undef`)
; CHECK-NEXT: B %bb.2
bb.0:
successors: %bb.1(0x80000000)
%0:gpr(s32) = G_IMPLICIT_DEF
%4:gpr(p0) = G_IMPLICIT_DEF
%8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
bb.1:
successors: %bb.2(0x80000000)
%6:gpr(s32) = G_IMPLICIT_DEF
%7:gpr(s32) = G_SELECT %0(s32), %6, %6
%1:gpr(s16) = G_TRUNC %7(s32)
bb.2:
successors: %bb.2(0x80000000)
%3:gpr(s16) = G_PHI %1(s16), %bb.1, %5(s16), %bb.2
%5:fpr(s16) = G_FPTRUNC %8(s32)
G_STORE %3(s16), %4(p0) :: (store (s16) into `ptr undef`)
G_BR %bb.2
...
---
name: test_loop_phi_gpr_to_fpr
alignment: 4
legalized: true
regBankSelected: true
selected: false
failedISel: false
tracksRegLiveness: true
liveins: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: test_loop_phi_gpr_to_fpr
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:gpr64common = IMPLICIT_DEF
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 2143289344
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF2:%[0-9]+]]:gpr32 = IMPLICIT_DEF
; CHECK-NEXT: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[DEF]], 0, implicit-def $nzcv
; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[DEF2]], [[DEF2]], 1, implicit $nzcv
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[CSELWr]]
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr16 = COPY [[COPY1]].hsub
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:fpr16 = PHI %7, %bb.2, [[COPY2]], %bb.1
; CHECK-NEXT: [[FCVTHSr:%[0-9]+]]:fpr16 = nofpexcept FCVTHSr [[COPY]]
; CHECK-NEXT: STRHui [[PHI]], [[DEF1]], 0 :: (store (s16) into `ptr undef`)
; CHECK-NEXT: B %bb.2
bb.0:
successors: %bb.1(0x80000000)
%0:gpr(s32) = G_IMPLICIT_DEF
%4:gpr(p0) = G_IMPLICIT_DEF
%8:fpr(s32) = G_FCONSTANT float 0x7FF8000000000000
bb.1:
successors: %bb.2(0x80000000)
%6:gpr(s32) = G_IMPLICIT_DEF
%7:gpr(s32) = G_SELECT %0(s32), %6, %6
%1:gpr(s16) = G_TRUNC %7(s32)
bb.2:
successors: %bb.2(0x80000000)
%3:fpr(s16) = G_PHI %5(s16), %bb.2, %1(s16), %bb.1
%5:fpr(s16) = G_FPTRUNC %8(s32)
G_STORE %3(s16), %4(p0) :: (store (s16) into `ptr undef`)
G_BR %bb.2
...
---
name: multiple_phis
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: multiple_phis
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.5(0x40000000)
; CHECK-NEXT: liveins: $w0, $w1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %ptr:gpr64sp = COPY $x2
; CHECK-NEXT: %cond_1:gpr32 = IMPLICIT_DEF
; CHECK-NEXT: %gpr_1:gpr32 = IMPLICIT_DEF
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY %gpr_1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[COPY]].hsub
; CHECK-NEXT: TBNZW %cond_1, 0, %bb.5
; CHECK-NEXT: B %bb.1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %cond_2:gpr32 = IMPLICIT_DEF
; CHECK-NEXT: TBNZW %cond_2, 0, %bb.3
; CHECK-NEXT: B %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %gpr_2:gpr32 = IMPLICIT_DEF
; CHECK-NEXT: B %bb.4
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %fpr:fpr16 = IMPLICIT_DEF
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4:
; CHECK-NEXT: successors: %bb.5(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %fp_phi:fpr16 = PHI %fpr, %bb.3, [[COPY1]], %bb.2
; CHECK-NEXT: %gp_phi1:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
; CHECK-NEXT: %gp_phi2:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
; CHECK-NEXT: %gp_phi3:gpr32 = PHI %gpr_1, %bb.3, %gpr_2, %bb.2
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, %fp_phi, %subreg.hsub
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.5:
; CHECK-NEXT: %use_fp_phi:gpr32 = PHI %gpr_1, %bb.0, [[COPY2]], %bb.4
; CHECK-NEXT: %use_gp_phi1:gpr32 = PHI %gpr_1, %bb.0, %gp_phi1, %bb.4
; CHECK-NEXT: %use_gp_phi2:gpr32 = PHI %gpr_1, %bb.0, %gp_phi2, %bb.4
; CHECK-NEXT: %use_gp_phi3:gpr32 = PHI %gpr_1, %bb.0, %gp_phi3, %bb.4
; CHECK-NEXT: STRHHui %use_fp_phi, %ptr, 0 :: (store (s16))
; CHECK-NEXT: STRHHui %use_gp_phi1, %ptr, 0 :: (store (s16))
; CHECK-NEXT: STRHHui %use_gp_phi2, %ptr, 0 :: (store (s16))
; CHECK-NEXT: STRHHui %use_gp_phi3, %ptr, 0 :: (store (s16))
; CHECK-NEXT: RET_ReallyLR
; The copy we insert in bb.4 should appear after all the phi instructions.
bb.1:
successors: %bb.2, %bb.6
liveins: $w0, $w1, $x2
%ptr:gpr(p0) = COPY $x2
%cond_1:gpr(s32) = G_IMPLICIT_DEF
%gpr_1:gpr(s16) = G_IMPLICIT_DEF
G_BRCOND %cond_1(s32), %bb.6
G_BR %bb.2
bb.2:
successors: %bb.3, %bb.4
%cond_2:gpr(s32) = G_IMPLICIT_DEF
G_BRCOND %cond_2(s32), %bb.4
G_BR %bb.3
bb.3:
%gpr_2:gpr(s16) = G_IMPLICIT_DEF
G_BR %bb.5
bb.4:
%fpr:fpr(s16) = G_IMPLICIT_DEF
bb.5:
%fp_phi:fpr(s16) = G_PHI %fpr(s16), %bb.4, %gpr_1(s16), %bb.3
%gp_phi1:gpr(s16) = G_PHI %gpr_1(s16), %bb.4, %gpr_2(s16), %bb.3
%gp_phi2:gpr(s16) = G_PHI %gpr_1(s16), %bb.4, %gpr_2(s16), %bb.3
%gp_phi3:gpr(s16) = G_PHI %gpr_1(s16), %bb.4, %gpr_2(s16), %bb.3
bb.6:
%use_fp_phi:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %fp_phi(s16), %bb.5
%use_gp_phi1:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %gp_phi1(s16), %bb.5
%use_gp_phi2:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %gp_phi2(s16), %bb.5
%use_gp_phi3:gpr(s16) = G_PHI %gpr_1(s16), %bb.1, %gp_phi3(s16), %bb.5
G_STORE %use_fp_phi(s16), %ptr(p0) :: (store (s16))
G_STORE %use_gp_phi1(s16), %ptr(p0) :: (store (s16))
G_STORE %use_gp_phi2(s16), %ptr(p0) :: (store (s16))
G_STORE %use_gp_phi3(s16), %ptr(p0) :: (store (s16))
RET_ReallyLR
...
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