302 lines
8.5 KiB
YAML
302 lines
8.5 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs -O0 -run-pass=instruction-select -global-isel-abort=1 %s -o - | FileCheck %s
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...
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---
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name: v2s32_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: gpr }
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- { id: 3, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v2s32_fpr
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; CHECK: liveins: $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK-NEXT: [[DUPi32_:%[0-9]+]]:fpr32 = DUPi32 [[INSERT_SUBREG]], 1
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; CHECK-NEXT: $s0 = COPY [[DUPi32_]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(<2 x s32>) = COPY $d0
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%2:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: v2s32_fpr_idx0
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v2s32_fpr_idx0
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; CHECK: liveins: $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]].ssub
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; CHECK-NEXT: $s0 = COPY [[COPY1]]
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; CHECK-NEXT: RET_ReallyLR implicit $s0
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%0:fpr(<2 x s32>) = COPY $d0
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%2:gpr(s64) = G_CONSTANT i64 0
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
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$s0 = COPY %1(s32)
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RET_ReallyLR implicit $s0
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...
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---
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name: v2s64_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: gpr }
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- { id: 3, class: fpr }
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v2s64_fpr
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 2
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; CHECK-NEXT: $d0 = COPY [[DUPi64_]]
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:fpr(<2 x s64>) = COPY $q0
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%2:gpr(s64) = G_CONSTANT i64 2
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s64) = G_EXTRACT_VECTOR_ELT %0(<2 x s64>), %3(s64)
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$d0 = COPY %1(s64)
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RET_ReallyLR implicit $d0
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...
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---
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name: v4s16_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: fpr }
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- { id: 1, class: fpr }
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- { id: 2, class: gpr }
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- { id: 3, class: fpr }
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: v4s16_fpr
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; CHECK: liveins: $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
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; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
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; CHECK-NEXT: RET_ReallyLR implicit $h0
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%0:fpr(<4 x s16>) = COPY $d0
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%2:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %3(s64)
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: v8s16_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v8s16_fpr
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
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; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
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; CHECK-NEXT: RET_ReallyLR implicit $h0
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%0:fpr(<8 x s16>) = COPY $q0
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%2:gpr(s64) = G_CONSTANT i64 1
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%3:fpr(s64) = COPY %2(s64)
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%1:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
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$h0 = COPY %1(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: v8s16_fpr_zext
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v8s16_fpr_zext
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
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; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
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; CHECK-NEXT: RET_ReallyLR implicit $h0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s64) = G_ZEXT %1
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%3:fpr(s64) = COPY %2(s64)
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%4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
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$h0 = COPY %4(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: v8s16_fpr_sext
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v8s16_fpr_sext
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
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; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
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; CHECK-NEXT: RET_ReallyLR implicit $h0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:gpr(s32) = G_CONSTANT i32 1
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%2:gpr(s64) = G_SEXT %1
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%3:fpr(s64) = COPY %2(s64)
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%4:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %3(s64)
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$h0 = COPY %4(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: v8s16_fpr_trunc
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v8s16_fpr_trunc
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[COPY]], 1
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; CHECK-NEXT: $h0 = COPY [[DUPi16_]]
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; CHECK-NEXT: RET_ReallyLR implicit $h0
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%0:fpr(<8 x s16>) = COPY $q0
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%1:gpr(s64) = G_CONSTANT i64 1
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%2:gpr(s32) = G_TRUNC %1
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%3:gpr(s64) = G_SEXT %2
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%4:fpr(s64) = COPY %3(s64)
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%5:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
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$h0 = COPY %5(s16)
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RET_ReallyLR implicit $h0
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...
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---
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name: v16s8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0' }
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body: |
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bb.1:
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liveins: $q0
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; CHECK-LABEL: name: v16s8
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[COPY]], 0
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; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:fpr(<16 x s8>) = COPY $q0
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%2:gpr(s64) = G_CONSTANT i64 0
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%1:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %2(s64)
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%4:gpr(s8) = COPY %1(s8)
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%3:gpr(s32) = G_ANYEXT %4(s8)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: v8s8
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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liveins:
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- { reg: '$q0' }
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body: |
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bb.1:
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liveins: $d0
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; CHECK-LABEL: name: v8s8
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; CHECK: liveins: $d0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK-NEXT: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[INSERT_SUBREG]], 0
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; CHECK-NEXT: $w0 = COPY [[UMOVvi8_]]
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; CHECK-NEXT: RET_ReallyLR implicit $w0
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%0:fpr(<8 x s8>) = COPY $d0
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%2:gpr(s64) = G_CONSTANT i64 0
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%1:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %2(s64)
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%4:gpr(s8) = COPY %1(s8)
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%3:gpr(s32) = G_ANYEXT %4(s8)
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$w0 = COPY %3(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: v2p0
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: v2p0
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; CHECK: liveins: $q0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK-NEXT: [[DUPi64_:%[0-9]+]]:fpr64 = DUPi64 [[COPY]], 1
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; CHECK-NEXT: $d0 = COPY [[DUPi64_]]
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; CHECK-NEXT: RET_ReallyLR implicit $d0
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%0:fpr(<2 x p0>) = COPY $q0
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%2:gpr(s64) = G_CONSTANT i64 1
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%1:fpr(p0) = G_EXTRACT_VECTOR_ELT %0(<2 x p0>), %2(s64)
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$d0 = COPY %1(p0)
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RET_ReallyLR implicit $d0
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...
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