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bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AArch64/GlobalISel/store-merging.mir
Sam Vervaeck 174b6f4d4e
Embed LLVM 18.1.8
2025-02-14 19:21:04 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=loadstore-opt -verify-machineinstrs %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
define void @test_simple_2xs8(i8* %ptr) {
%addr11 = bitcast i8* %ptr to i8*
store i8 4, i8* %addr11, align 1
%addr2 = getelementptr i8, i8* %ptr, i64 1
store i8 5, i8* %addr2, align 1
ret void
}
define void @test_simple_2xs16(i16* %ptr) {
%addr11 = bitcast i16* %ptr to i16*
store i16 4, i16* %addr11, align 2
%addr2 = getelementptr i16, i16* %ptr, i64 1
store i16 5, i16* %addr2, align 2
ret void
}
define void @test_simple_4xs16(i16* %ptr) {
%addr11 = bitcast i16* %ptr to i16*
store i16 4, i16* %addr11, align 2
%addr2 = getelementptr i16, i16* %ptr, i64 1
store i16 5, i16* %addr2, align 2
%addr3 = getelementptr i16, i16* %ptr, i64 2
store i16 9, i16* %addr3, align 2
%addr4 = getelementptr i16, i16* %ptr, i64 3
store i16 14, i16* %addr4, align 2
ret void
}
define void @test_simple_2xs32(i32* %ptr) {
%addr11 = bitcast i32* %ptr to i32*
store i32 4, i32* %addr11, align 4
%addr2 = getelementptr i32, i32* %ptr, i64 1
store i32 5, i32* %addr2, align 4
ret void
}
define void @test_simple_2xs64_illegal(i64* %ptr) {
%addr11 = bitcast i64* %ptr to i64*
store i64 4, i64* %addr11, align 8
%addr2 = getelementptr i64, i64* %ptr, i64 1
store i64 5, i64* %addr2, align 8
ret void
}
define void @test_simple_vector(<2 x i16>* %ptr) {
%addr11 = bitcast <2 x i16>* %ptr to <2 x i16>*
store <2 x i16> <i16 4, i16 7>, <2 x i16>* %addr11, align 4
%addr2 = getelementptr <2 x i16>, <2 x i16>* %ptr, i64 1
store <2 x i16> <i16 5, i16 8>, <2 x i16>* %addr2, align 4
ret void
}
define i32 @test_unknown_alias(i32* %ptr, i32* %aliasptr) {
%addr11 = bitcast i32* %ptr to i32*
store i32 4, i32* %addr11, align 4
%ld = load i32, i32* %aliasptr, align 4
%addr2 = getelementptr i32, i32* %ptr, i64 1
store i32 5, i32* %addr2, align 4
ret i32 %ld
}
define void @test_2x_2xs32(i32* %ptr, i32* %ptr2) {
%addr11 = bitcast i32* %ptr to i32*
store i32 4, i32* %addr11, align 4
%addr2 = getelementptr i32, i32* %ptr, i64 1
store i32 5, i32* %addr2, align 4
%addr32 = bitcast i32* %ptr2 to i32*
store i32 9, i32* %addr32, align 4
%addr4 = getelementptr i32, i32* %ptr2, i64 1
store i32 17, i32* %addr4, align 4
ret void
}
define void @test_simple_var_2xs8(i8* %ptr, i8 %v1, i8 %v2) {
%addr11 = bitcast i8* %ptr to i8*
store i8 %v1, i8* %addr11, align 1
%addr2 = getelementptr i8, i8* %ptr, i64 1
store i8 %v2, i8* %addr2, align 1
ret void
}
define void @test_simple_var_2xs16(i16* %ptr, i16 %v1, i16 %v2) {
%addr11 = bitcast i16* %ptr to i16*
store i16 %v1, i16* %addr11, align 2
%addr2 = getelementptr i16, i16* %ptr, i64 1
store i16 %v2, i16* %addr2, align 2
ret void
}
define void @test_simple_var_2xs32(i32* %ptr, i32 %v1, i32 %v2) {
%addr11 = bitcast i32* %ptr to i32*
store i32 %v1, i32* %addr11, align 4
%addr2 = getelementptr i32, i32* %ptr, i64 1
store i32 %v2, i32* %addr2, align 4
ret void
}
define void @test_alias_4xs16(i16* %ptr, i16* %ptr2) {
%addr11 = bitcast i16* %ptr to i16*
store i16 4, i16* %addr11, align 2
%addr2 = getelementptr i16, i16* %ptr, i64 1
store i16 5, i16* %addr2, align 2
%addr3 = getelementptr i16, i16* %ptr, i64 2
store i16 9, i16* %addr3, align 2
store i16 0, i16* %ptr2, align 2
%addr4 = getelementptr i16, i16* %ptr, i64 3
store i16 14, i16* %addr4, align 2
ret void
}
define void @test_alias2_4xs16(i16* %ptr, i16* %ptr2, i16* %ptr3) {
%addr11 = bitcast i16* %ptr to i16*
store i16 4, i16* %addr11, align 2
%addr2 = getelementptr i16, i16* %ptr, i64 1
store i16 0, i16* %ptr3, align 2
store i16 5, i16* %addr2, align 2
%addr3 = getelementptr i16, i16* %ptr, i64 2
store i16 9, i16* %addr3, align 2
store i16 0, i16* %ptr2, align 2
%addr4 = getelementptr i16, i16* %ptr, i64 3
store i16 14, i16* %addr4, align 2
ret void
}
define void @test_alias3_4xs16(i16* %ptr, i16* %ptr2, i16* %ptr3, i16* %ptr4) {
%addr11 = bitcast i16* %ptr to i16*
store i16 4, i16* %addr11, align 2
%addr2 = getelementptr i16, i16* %ptr, i64 1
store i16 0, i16* %ptr3, align 2
store i16 5, i16* %addr2, align 2
store i16 0, i16* %ptr4, align 2
%addr3 = getelementptr i16, i16* %ptr, i64 2
store i16 9, i16* %addr3, align 2
store i16 0, i16* %ptr2, align 2
%addr4 = getelementptr i16, i16* %ptr, i64 3
store i16 14, i16* %addr4, align 2
ret void
}
define i32 @test_alias_allocas_2xs32(i32* %ptr) {
%a1 = alloca [6 x i32], align 4
%a2 = alloca i32, align 4
%addr11 = bitcast [6 x i32]* %a1 to i32*
store i32 4, i32* %addr11, align 4
%ld = load i32, i32* %a2, align 4
%addr2 = getelementptr [6 x i32], [6 x i32]* %a1, i64 0, i32 1
store i32 5, i32* %addr2, align 4
ret i32 %ld
}
define void @test_simple_2xs32_with_align(i32* %ptr) {
%addr11 = bitcast i32* %ptr to i32*
store i32 4, i32* %addr11, align 4
%addr2 = getelementptr i32, i32* %ptr, i64 1
store i32 5, i32* %addr2, align 4
ret void
}
@G = external global [10 x i32]
define void @invalid_zero_offset_no_merge(i64 %0) {
%2 = getelementptr [10 x i32], ptr @G, i64 0, i64 %0
store i32 0, ptr %2, align 4
store i32 0, ptr getelementptr inbounds ([10 x i32], ptr @G, i64 0, i64 1), align 4
ret void
}
...
---
name: test_simple_2xs8
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $x0
; CHECK-LABEL: name: test_simple_2xs8
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 4
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 5
; CHECK-NEXT: G_STORE [[C]](s8), [[COPY]](p0) :: (store (s8) into %ir.addr11)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK-NEXT: G_STORE [[C1]](s8), [[PTR_ADD]](p0) :: (store (s8) into %ir.addr2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s8) = G_CONSTANT i8 4
%4:_(s8) = G_CONSTANT i8 5
G_STORE %1(s8), %0(p0) :: (store (s8) into %ir.addr11)
%2:_(s64) = G_CONSTANT i64 1
%3:_(p0) = G_PTR_ADD %0, %2(s64)
G_STORE %4(s8), %3(p0) :: (store (s8) into %ir.addr2)
RET_ReallyLR
...
---
name: test_simple_2xs16
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $x0
; CHECK-LABEL: name: test_simple_2xs16
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 327684
; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11, align 2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s16) = G_CONSTANT i16 4
%4:_(s16) = G_CONSTANT i16 5
G_STORE %1(s16), %0(p0) :: (store (s16) into %ir.addr11)
%2:_(s64) = G_CONSTANT i64 2
%3:_(p0) = G_PTR_ADD %0, %2(s64)
G_STORE %4(s16), %3(p0) :: (store (s16) into %ir.addr2)
RET_ReallyLR
...
---
name: test_simple_4xs16
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $x0
; CHECK-LABEL: name: test_simple_4xs16
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 3940688328982532
; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11, align 2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s16) = G_CONSTANT i16 4
%4:_(s16) = G_CONSTANT i16 5
%7:_(s16) = G_CONSTANT i16 9
%10:_(s16) = G_CONSTANT i16 14
G_STORE %1(s16), %0(p0) :: (store (s16) into %ir.addr11)
%2:_(s64) = G_CONSTANT i64 2
%3:_(p0) = G_PTR_ADD %0, %2(s64)
G_STORE %4(s16), %3(p0) :: (store (s16) into %ir.addr2)
%5:_(s64) = G_CONSTANT i64 4
%6:_(p0) = G_PTR_ADD %0, %5(s64)
G_STORE %7(s16), %6(p0) :: (store (s16) into %ir.addr3)
%8:_(s64) = G_CONSTANT i64 6
%9:_(p0) = G_PTR_ADD %0, %8(s64)
G_STORE %10(s16), %9(p0) :: (store (s16) into %ir.addr4)
RET_ReallyLR
...
---
name: test_simple_2xs32
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $x0
; CHECK-LABEL: name: test_simple_2xs32
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21474836484
; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 4
%4:_(s32) = G_CONSTANT i32 5
G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.addr11)
%2:_(s64) = G_CONSTANT i64 4
%3:_(p0) = G_PTR_ADD %0, %2(s64)
G_STORE %4(s32), %3(p0) :: (store (s32) into %ir.addr2)
RET_ReallyLR
...
---
name: test_simple_2xs64_illegal
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $x0
; CHECK-LABEL: name: test_simple_2xs64_illegal
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK-NEXT: G_STORE [[C1]](s64), [[PTR_ADD]](p0) :: (store (s64) into %ir.addr2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s64) = G_CONSTANT i64 4
%4:_(s64) = G_CONSTANT i64 5
G_STORE %1(s64), %0(p0) :: (store (s64) into %ir.addr11)
%2:_(s64) = G_CONSTANT i64 8
%3:_(p0) = G_PTR_ADD %0, %2(s64)
G_STORE %4(s64), %3(p0) :: (store (s64) into %ir.addr2)
RET_ReallyLR
...
---
name: test_simple_vector
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $x0
; CHECK-LABEL: name: test_simple_vector
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 7
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C1]](s16)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 5
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C2]](s16), [[C3]](s16)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s16>), [[COPY]](p0) :: (store (<2 x s16>) into %ir.addr11)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<2 x s16>), [[PTR_ADD]](p0) :: (store (<2 x s16>) into %ir.addr2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%2:_(s16) = G_CONSTANT i16 4
%3:_(s16) = G_CONSTANT i16 7
%1:_(<2 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16)
%7:_(s16) = G_CONSTANT i16 5
%8:_(s16) = G_CONSTANT i16 8
%6:_(<2 x s16>) = G_BUILD_VECTOR %7(s16), %8(s16)
G_STORE %1(<2 x s16>), %0(p0) :: (store (<2 x s16>) into %ir.addr11)
%4:_(s64) = G_CONSTANT i64 4
%5:_(p0) = G_PTR_ADD %0, %4(s64)
G_STORE %6(<2 x s16>), %5(p0) :: (store (<2 x s16>) into %ir.addr2)
RET_ReallyLR
...
---
name: test_unknown_alias
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$x1' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $x0, $x1
; CHECK-LABEL: name: test_unknown_alias
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p0) :: (load (s32) from %ir.aliasptr)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2)
; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
%2:_(s32) = G_CONSTANT i32 4
%6:_(s32) = G_CONSTANT i32 5
G_STORE %2(s32), %0(p0) :: (store (s32) into %ir.addr11)
%3:_(s32) = G_LOAD %1(p0) :: (load (s32) from %ir.aliasptr)
%4:_(s64) = G_CONSTANT i64 4
%5:_(p0) = G_PTR_ADD %0, %4(s64)
G_STORE %6(s32), %5(p0) :: (store (s32) into %ir.addr2)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: test_2x_2xs32
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$x1' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $x0, $x1
; CHECK-LABEL: name: test_2x_2xs32
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 73014444041
; CHECK-NEXT: G_STORE [[C3]](s64), [[COPY1]](p0) :: (store (s64) into %ir.addr32, align 4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
%2:_(s32) = G_CONSTANT i32 4
%5:_(s32) = G_CONSTANT i32 5
%6:_(s32) = G_CONSTANT i32 9
%8:_(s32) = G_CONSTANT i32 17
G_STORE %2(s32), %0(p0) :: (store (s32) into %ir.addr11)
%3:_(s64) = G_CONSTANT i64 4
%4:_(p0) = G_PTR_ADD %0, %3(s64)
G_STORE %5(s32), %4(p0) :: (store (s32) into %ir.addr2)
G_STORE %6(s32), %1(p0) :: (store (s32) into %ir.addr32)
%7:_(p0) = G_PTR_ADD %1, %3(s64)
G_STORE %8(s32), %7(p0) :: (store (s32) into %ir.addr4)
RET_ReallyLR
...
---
name: test_simple_var_2xs8
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$w1' }
- { reg: '$w2' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $w1, $w2, $x0
; CHECK-LABEL: name: test_simple_var_2xs8
; CHECK: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
; CHECK-NEXT: G_STORE [[TRUNC]](s8), [[COPY]](p0) :: (store (s8) into %ir.addr11)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CHECK-NEXT: G_STORE [[TRUNC1]](s8), [[PTR_ADD]](p0) :: (store (s8) into %ir.addr2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%3:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s32) = COPY $w2
%2:_(s8) = G_TRUNC %4(s32)
G_STORE %1(s8), %0(p0) :: (store (s8) into %ir.addr11)
%5:_(s64) = G_CONSTANT i64 1
%6:_(p0) = G_PTR_ADD %0, %5(s64)
G_STORE %2(s8), %6(p0) :: (store (s8) into %ir.addr2)
RET_ReallyLR
...
---
name: test_simple_var_2xs16
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$w1' }
- { reg: '$w2' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $w1, $w2, $x0
; CHECK-LABEL: name: test_simple_var_2xs16
; CHECK: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY]](p0) :: (store (s16) into %ir.addr11)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CHECK-NEXT: G_STORE [[TRUNC1]](s16), [[PTR_ADD]](p0) :: (store (s16) into %ir.addr2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%3:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s32) = COPY $w2
%2:_(s16) = G_TRUNC %4(s32)
G_STORE %1(s16), %0(p0) :: (store (s16) into %ir.addr11)
%5:_(s64) = G_CONSTANT i64 2
%6:_(p0) = G_PTR_ADD %0, %5(s64)
G_STORE %2(s16), %6(p0) :: (store (s16) into %ir.addr2)
RET_ReallyLR
...
---
name: test_simple_var_2xs32
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$w1' }
- { reg: '$w2' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $w1, $w2, $x0
; CHECK-LABEL: name: test_simple_var_2xs32
; CHECK: liveins: $w1, $w2, $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CHECK-NEXT: G_STORE [[COPY2]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = COPY $w1
%2:_(s32) = COPY $w2
G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.addr11)
%3:_(s64) = G_CONSTANT i64 4
%4:_(p0) = G_PTR_ADD %0, %3(s64)
G_STORE %2(s32), %4(p0) :: (store (s32) into %ir.addr2)
RET_ReallyLR
...
---
name: test_alias_4xs16
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$x1' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
# The store to ptr2 prevents merging into a single store.
# We can still merge the stores into addr1 and addr2.
body: |
bb.1 (%ir-block.0):
liveins: $x0, $x1
; CHECK-LABEL: name: test_alias_4xs16
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 14
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 327684
; CHECK-NEXT: G_STORE [[C3]](s32), [[COPY]](p0) :: (store (s32) into %ir.addr11, align 2)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C4]](s64)
; CHECK-NEXT: G_STORE [[C]](s16), [[PTR_ADD]](p0) :: (store (s16) into %ir.addr3)
; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY1]](p0) :: (store (s16) into %ir.ptr2)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64)
; CHECK-NEXT: G_STORE [[C2]](s16), [[PTR_ADD1]](p0) :: (store (s16) into %ir.addr4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
%2:_(s16) = G_CONSTANT i16 4
%5:_(s16) = G_CONSTANT i16 5
%8:_(s16) = G_CONSTANT i16 9
%9:_(s16) = G_CONSTANT i16 0
%12:_(s16) = G_CONSTANT i16 14
G_STORE %2(s16), %0(p0) :: (store (s16) into %ir.addr11)
%3:_(s64) = G_CONSTANT i64 2
%4:_(p0) = G_PTR_ADD %0, %3(s64)
G_STORE %5(s16), %4(p0) :: (store (s16) into %ir.addr2)
%6:_(s64) = G_CONSTANT i64 4
%7:_(p0) = G_PTR_ADD %0, %6(s64)
G_STORE %8(s16), %7(p0) :: (store (s16) into %ir.addr3)
G_STORE %9(s16), %1(p0) :: (store (s16) into %ir.ptr2)
%10:_(s64) = G_CONSTANT i64 6
%11:_(p0) = G_PTR_ADD %0, %10(s64)
G_STORE %12(s16), %11(p0) :: (store (s16) into %ir.addr4)
RET_ReallyLR
...
---
name: test_alias2_4xs16
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$x1' }
- { reg: '$x2' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
# Here store of 5 and 9 can be merged, others have aliasing barriers.
body: |
bb.1 (%ir-block.0):
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: test_alias2_4xs16
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 14
; CHECK-NEXT: G_STORE [[C]](s16), [[COPY]](p0) :: (store (s16) into %ir.addr11)
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C3]](s64)
; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY2]](p0) :: (store (s16) into %ir.ptr3)
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 589829
; CHECK-NEXT: G_STORE [[C4]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.addr2, align 2)
; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY1]](p0) :: (store (s16) into %ir.ptr2)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64)
; CHECK-NEXT: G_STORE [[C2]](s16), [[PTR_ADD1]](p0) :: (store (s16) into %ir.addr4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
%2:_(p0) = COPY $x2
%3:_(s16) = G_CONSTANT i16 4
%6:_(s16) = G_CONSTANT i16 0
%7:_(s16) = G_CONSTANT i16 5
%10:_(s16) = G_CONSTANT i16 9
%13:_(s16) = G_CONSTANT i16 14
G_STORE %3(s16), %0(p0) :: (store (s16) into %ir.addr11)
%4:_(s64) = G_CONSTANT i64 2
%5:_(p0) = G_PTR_ADD %0, %4(s64)
G_STORE %6(s16), %2(p0) :: (store (s16) into %ir.ptr3)
G_STORE %7(s16), %5(p0) :: (store (s16) into %ir.addr2)
%8:_(s64) = G_CONSTANT i64 4
%9:_(p0) = G_PTR_ADD %0, %8(s64)
G_STORE %10(s16), %9(p0) :: (store (s16) into %ir.addr3)
G_STORE %6(s16), %1(p0) :: (store (s16) into %ir.ptr2)
%11:_(s64) = G_CONSTANT i64 6
%12:_(p0) = G_PTR_ADD %0, %11(s64)
G_STORE %13(s16), %12(p0) :: (store (s16) into %ir.addr4)
RET_ReallyLR
...
---
name: test_alias3_4xs16
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
- { reg: '$x1' }
- { reg: '$x2' }
- { reg: '$x3' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
# No merging can be done here.
body: |
bb.1 (%ir-block.0):
liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_alias3_4xs16
; CHECK: liveins: $x0, $x1, $x2, $x3
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY $x3
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 0
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 5
; CHECK-NEXT: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; CHECK-NEXT: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 14
; CHECK-NEXT: G_STORE [[C]](s16), [[COPY]](p0) :: (store (s16) into %ir.addr11)
; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C5]](s64)
; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY2]](p0) :: (store (s16) into %ir.ptr3)
; CHECK-NEXT: G_STORE [[C2]](s16), [[PTR_ADD]](p0) :: (store (s16) into %ir.addr2)
; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY3]](p0) :: (store (s16) into %ir.ptr4)
; CHECK-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s64)
; CHECK-NEXT: G_STORE [[C3]](s16), [[PTR_ADD1]](p0) :: (store (s16) into %ir.addr3)
; CHECK-NEXT: G_STORE [[C1]](s16), [[COPY1]](p0) :: (store (s16) into %ir.ptr2)
; CHECK-NEXT: [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C7]](s64)
; CHECK-NEXT: G_STORE [[C4]](s16), [[PTR_ADD2]](p0) :: (store (s16) into %ir.addr4)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(p0) = COPY $x1
%2:_(p0) = COPY $x2
%3:_(p0) = COPY $x3
%4:_(s16) = G_CONSTANT i16 4
%7:_(s16) = G_CONSTANT i16 0
%8:_(s16) = G_CONSTANT i16 5
%11:_(s16) = G_CONSTANT i16 9
%14:_(s16) = G_CONSTANT i16 14
G_STORE %4(s16), %0(p0) :: (store (s16) into %ir.addr11)
%5:_(s64) = G_CONSTANT i64 2
%6:_(p0) = G_PTR_ADD %0, %5(s64)
G_STORE %7(s16), %2(p0) :: (store (s16) into %ir.ptr3)
G_STORE %8(s16), %6(p0) :: (store (s16) into %ir.addr2)
G_STORE %7(s16), %3(p0) :: (store (s16) into %ir.ptr4)
%9:_(s64) = G_CONSTANT i64 4
%10:_(p0) = G_PTR_ADD %0, %9(s64)
G_STORE %11(s16), %10(p0) :: (store (s16) into %ir.addr3)
G_STORE %7(s16), %1(p0) :: (store (s16) into %ir.ptr2)
%12:_(s64) = G_CONSTANT i64 6
%13:_(p0) = G_PTR_ADD %0, %12(s64)
G_STORE %14(s16), %13(p0) :: (store (s16) into %ir.addr4)
RET_ReallyLR
...
---
name: test_alias_allocas_2xs32
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 4
stack:
- { id: 0, name: a1, size: 24, alignment: 4 }
- { id: 1, name: a2, size: 4, alignment: 4 }
machineFunctionInfo: {}
# Can merge because the load is from a different alloca and can't alias.
body: |
bb.1 (%ir-block.0):
liveins: $x0
; CHECK-LABEL: name: test_alias_allocas_2xs32
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0.a1
; CHECK-NEXT: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.1.a2
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (dereferenceable load (s32) from %ir.a2)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21474836484
; CHECK-NEXT: G_STORE [[C]](s64), [[FRAME_INDEX]](p0) :: (store (s64) into %ir.addr11, align 4)
; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%3:_(s32) = G_CONSTANT i32 4
%7:_(s32) = G_CONSTANT i32 5
%1:_(p0) = G_FRAME_INDEX %stack.0.a1
%2:_(p0) = G_FRAME_INDEX %stack.1.a2
G_STORE %3(s32), %1(p0) :: (store (s32) into %ir.addr11)
%4:_(s32) = G_LOAD %2(p0) :: (dereferenceable load (s32) from %ir.a2)
%5:_(s64) = G_CONSTANT i64 4
%6:_(p0) = G_PTR_ADD %1, %5(s64)
G_STORE %7(s32), %6(p0) :: (store (s32) into %ir.addr2)
$w0 = COPY %4(s32)
RET_ReallyLR implicit $w0
...
---
name: test_simple_2xs32_with_align
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.0):
liveins: $x0
; CHECK-LABEL: name: test_simple_2xs32_with_align
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 21474836484
; CHECK-NEXT: G_STORE [[C]](s64), [[COPY]](p0) :: (store (s64) into %ir.addr11, align 2)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1:_(s32) = G_CONSTANT i32 4
%4:_(s32) = G_CONSTANT i32 5
G_STORE %1(s32), %0(p0) :: (store (s32) into %ir.addr11, align 2)
%2:_(s64) = G_CONSTANT i64 4
%3:_(p0) = G_PTR_ADD %0, %2(s64)
G_STORE %4(s32), %3(p0) :: (store (s32) into %ir.addr2, align 2)
RET_ReallyLR
...
---
name: invalid_zero_offset_no_merge
alignment: 4
tracksRegLiveness: true
liveins:
- { reg: '$x0' }
frameInfo:
maxAlignment: 1
machineFunctionInfo: {}
body: |
bb.1 (%ir-block.1):
liveins: $x0
; CHECK-LABEL: name: invalid_zero_offset_no_merge
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[C]](s64)
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @G
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[SHL]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD]](p0) :: (store (s32) into %ir.2)
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw G_PTR_ADD [[GV]], [[C2]](s64)
; CHECK-NEXT: G_STORE [[C1]](s32), [[PTR_ADD1]](p0) :: (store (s32) into `ptr getelementptr inbounds ([10 x i32], ptr @G, i64 0, i64 1)`)
; CHECK-NEXT: RET_ReallyLR
%0:_(s64) = COPY $x0
%9:_(s64) = G_CONSTANT i64 2
%3:_(s64) = G_SHL %0, %9(s64)
%1:_(p0) = G_GLOBAL_VALUE @G
%4:_(p0) = G_PTR_ADD %1, %3(s64)
%6:_(s32) = G_CONSTANT i32 0
G_STORE %6(s32), %4(p0) :: (store (s32) into %ir.2)
%8:_(s64) = G_CONSTANT i64 4
%7:_(p0) = nuw G_PTR_ADD %1, %8(s64)
G_STORE %6(s32), %7(p0) :: (store (s32) into `ptr getelementptr inbounds ([10 x i32], ptr @G, i64 0, i64 1)`)
RET_ReallyLR
...
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