128 lines
3.2 KiB
LLVM
128 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define i32 @i8_i32(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: i8_i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: smov w0, v0.b[15]
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; CHECK-NEXT: ret
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entry:
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%elt = extractelement <vscale x 16 x i8> %a, i32 15
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%conv = sext i8 %elt to i32
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ret i32 %conv
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}
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define i64 @i8_i64(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: i8_i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: smov x0, v0.b[15]
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; CHECK-NEXT: ret
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entry:
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%elt = extractelement <vscale x 16 x i8> %a, i32 15
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%conv = sext i8 %elt to i64
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ret i64 %conv
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}
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define i32 @i16_i32(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: i16_i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: smov w0, v0.h[7]
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; CHECK-NEXT: ret
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entry:
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%elt = extractelement <vscale x 8 x i16> %a, i32 7
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%conv = sext i16 %elt to i32
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ret i32 %conv
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}
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define i64 @i16_i64(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: i16_i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: smov x0, v0.h[7]
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; CHECK-NEXT: ret
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entry:
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%elt = extractelement <vscale x 8 x i16> %a, i32 7
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%conv = sext i16 %elt to i64
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ret i64 %conv
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}
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define i64 @i32_i64(<vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: i32_i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: smov x0, v0.s[3]
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; CHECK-NEXT: ret
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entry:
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%elt = extractelement <vscale x 4 x i32> %a, i32 3
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%conv = sext i32 %elt to i64
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ret i64 %conv
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}
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; NOTE: Testing out-of-range indices
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define i32 @i8_i32_oor(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: i8_i32_oor:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.b, z0.b[16]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: sxtb w0, w8
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; CHECK-NEXT: ret
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entry:
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%elt = extractelement <vscale x 16 x i8> %a, i32 16
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%conv = sext i8 %elt to i32
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ret i32 %conv
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}
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define i64 @i8_i64_oor(<vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: i8_i64_oor:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.b, z0.b[16]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: sxtb x0, w8
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; CHECK-NEXT: ret
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entry:
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%elt = extractelement <vscale x 16 x i8> %a, i32 16
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%conv = sext i8 %elt to i64
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ret i64 %conv
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}
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define i32 @i16_i32_oor(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: i16_i32_oor:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.h, z0.h[8]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: sxth w0, w8
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; CHECK-NEXT: ret
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entry:
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%elt = extractelement <vscale x 8 x i16> %a, i32 8
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%conv = sext i16 %elt to i32
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ret i32 %conv
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}
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define i64 @i16_i64_oor(<vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: i16_i64_oor:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.h, z0.h[8]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: sxth x0, w8
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; CHECK-NEXT: ret
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entry:
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%elt = extractelement <vscale x 8 x i16> %a, i32 8
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%conv = sext i16 %elt to i64
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ret i64 %conv
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}
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define i64 @i32_i64_oor(<vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: i32_i64_oor:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov z0.s, z0.s[4]
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: sxtw x0, w8
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; CHECK-NEXT: ret
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entry:
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%elt = extractelement <vscale x 4 x i32> %a, i32 4
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%conv = sext i32 %elt to i64
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ret i64 %conv
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}
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attributes #0 = { "target-features"="+sve" }
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