551 lines
15 KiB
LLVM
551 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-enable-collect-loh=false -aarch64-enable-sink-fold=true < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-enable-collect-loh=false -aarch64-enable-sink-fold=true -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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@board = common global [400 x i8] zeroinitializer, align 1
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@next_string = common global i32 0, align 4
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@string_number = common global [400 x i32] zeroinitializer, align 4
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; Function Attrs: nounwind ssp
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define void @new_position(i32 %pos) {
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; CHECK-SD-LABEL: new_position:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: adrp x8, _board@GOTPAGE
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; CHECK-SD-NEXT: ; kill: def $w0 killed $w0 def $x0
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; CHECK-SD-NEXT: ldr x8, [x8, _board@GOTPAGEOFF]
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; CHECK-SD-NEXT: ldrb w8, [x8, w0, sxtw]
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; CHECK-SD-NEXT: sub w8, w8, #1
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; CHECK-SD-NEXT: cmp w8, #1
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; CHECK-SD-NEXT: b.hi LBB0_2
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; CHECK-SD-NEXT: ; %bb.1: ; %if.then
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; CHECK-SD-NEXT: adrp x8, _next_string@GOTPAGE
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; CHECK-SD-NEXT: adrp x9, _string_number@GOTPAGE
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; CHECK-SD-NEXT: ldr x8, [x8, _next_string@GOTPAGEOFF]
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; CHECK-SD-NEXT: ldr x9, [x9, _string_number@GOTPAGEOFF]
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; CHECK-SD-NEXT: ldr w8, [x8]
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; CHECK-SD-NEXT: str w8, [x9, w0, sxtw #2]
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; CHECK-SD-NEXT: LBB0_2: ; %if.end
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: new_position:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: adrp x8, _board@GOTPAGE
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; CHECK-GI-NEXT: ldr x8, [x8, _board@GOTPAGEOFF]
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; CHECK-GI-NEXT: ldrb w8, [x8, w0, sxtw]
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; CHECK-GI-NEXT: sub w8, w8, #1
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; CHECK-GI-NEXT: cmp w8, #2
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; CHECK-GI-NEXT: b.hs LBB0_2
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; CHECK-GI-NEXT: ; %bb.1: ; %if.then
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; CHECK-GI-NEXT: adrp x8, _next_string@GOTPAGE
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; CHECK-GI-NEXT: adrp x9, _string_number@GOTPAGE
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; CHECK-GI-NEXT: ldr x8, [x8, _next_string@GOTPAGEOFF]
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; CHECK-GI-NEXT: ldr x9, [x9, _string_number@GOTPAGEOFF]
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; CHECK-GI-NEXT: ldr w8, [x8]
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; CHECK-GI-NEXT: str w8, [x9, w0, sxtw #2]
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; CHECK-GI-NEXT: LBB0_2: ; %if.end
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; CHECK-GI-NEXT: ret
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entry:
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%idxprom = sext i32 %pos to i64
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%arrayidx = getelementptr inbounds [400 x i8], ptr @board, i64 0, i64 %idxprom
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%tmp = load i8, ptr %arrayidx, align 1
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%.off = add i8 %tmp, -1
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%switch = icmp ult i8 %.off, 2
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br i1 %switch, label %if.then, label %if.end
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if.then: ; preds = %entry
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%tmp1 = load i32, ptr @next_string, align 4
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%arrayidx8 = getelementptr inbounds [400 x i32], ptr @string_number, i64 0, i64 %idxprom
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store i32 %tmp1, ptr %arrayidx8, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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ret void
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}
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define zeroext i1 @test8_0(i8 zeroext %x) align 2 {
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; CHECK-LABEL: test8_0:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: add w8, w0, #74
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; CHECK-NEXT: and w8, w8, #0xff
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; CHECK-NEXT: cmp w8, #236
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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entry:
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%0 = add i8 %x, 74
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%1 = icmp ult i8 %0, -20
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test8_1(i8 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test8_1:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: sub w8, w0, #10
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; CHECK-SD-NEXT: cmp w8, #89
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; CHECK-SD-NEXT: cset w0, hi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test8_1:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: sub w8, w0, #10
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; CHECK-GI-NEXT: cmp w8, #90
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; CHECK-GI-NEXT: cset w0, hs
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i8 %x, 246
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%1 = icmp uge i8 %0, 90
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test8_2(i8 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test8_2:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: cmp w0, #208
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test8_2:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: sub w8, w0, #29
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; CHECK-GI-NEXT: and w8, w8, #0xff
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; CHECK-GI-NEXT: cmp w8, #179
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; CHECK-GI-NEXT: cset w0, ne
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i8 %x, 227
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%1 = icmp ne i8 %0, 179
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test8_3(i8 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test8_3:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: cmp w0, #209
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; CHECK-SD-NEXT: cset w0, eq
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test8_3:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: sub w8, w0, #55
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; CHECK-GI-NEXT: and w8, w8, #0xff
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; CHECK-GI-NEXT: cmp w8, #154
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; CHECK-GI-NEXT: cset w0, eq
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i8 %x, 201
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%1 = icmp eq i8 %0, 154
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test8_4(i8 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test8_4:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: cmp w0, #39
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test8_4:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: sub w8, w0, #79
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; CHECK-GI-NEXT: and w8, w8, #0xff
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; CHECK-GI-NEXT: cmp w8, #216
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; CHECK-GI-NEXT: cset w0, ne
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i8 %x, -79
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%1 = icmp ne i8 %0, -40
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test8_5(i8 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test8_5:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: sub w8, w0, #123
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; CHECK-SD-NEXT: cmn w8, #106
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; CHECK-SD-NEXT: cset w0, hi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test8_5:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: sub w8, w0, #123
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; CHECK-GI-NEXT: cmn w8, #105
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; CHECK-GI-NEXT: cset w0, hs
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i8 %x, 133
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%1 = icmp uge i8 %0, -105
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test8_6(i8 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test8_6:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: sub w8, w0, #58
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; CHECK-SD-NEXT: cmp w8, #154
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; CHECK-SD-NEXT: cset w0, hi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test8_6:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: sub w8, w0, #58
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; CHECK-GI-NEXT: cmp w8, #155
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; CHECK-GI-NEXT: cset w0, hs
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i8 %x, -58
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%1 = icmp uge i8 %0, 155
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test8_7(i8 zeroext %x) align 2 {
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; CHECK-LABEL: test8_7:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: sub w8, w0, #31
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; CHECK-NEXT: cmp w8, #124
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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entry:
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%0 = add i8 %x, 225
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%1 = icmp ult i8 %0, 124
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test8_8(i8 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test8_8:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: cmp w0, #66
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test8_8:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: sub w8, w0, #66
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; CHECK-GI-NEXT: cmp w8, #1
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; CHECK-GI-NEXT: cset w0, hs
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i8 %x, 190
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%1 = icmp uge i8 %0, 1
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test16_0(i16 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test16_0:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: mov w8, #5086 ; =0x13de
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; CHECK-SD-NEXT: cmp w0, w8
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test16_0:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: mov w8, #18547 ; =0x4873
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; CHECK-GI-NEXT: mov w9, #23633 ; =0x5c51
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; CHECK-GI-NEXT: add w8, w0, w8
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; CHECK-GI-NEXT: cmp w9, w8, uxth
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; CHECK-GI-NEXT: cset w0, ne
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i16 %x, -46989
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%1 = icmp ne i16 %0, -41903
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test16_2(i16 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test16_2:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: mov w8, #16882 ; =0x41f2
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; CHECK-SD-NEXT: mov w9, #40700 ; =0x9efc
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; CHECK-SD-NEXT: add w8, w0, w8
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; CHECK-SD-NEXT: cmp w9, w8, uxth
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; CHECK-SD-NEXT: cset w0, hi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test16_2:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: mov w8, #16882 ; =0x41f2
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; CHECK-GI-NEXT: mov w9, #40699 ; =0x9efb
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; CHECK-GI-NEXT: add w8, w0, w8
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; CHECK-GI-NEXT: cmp w9, w8, uxth
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; CHECK-GI-NEXT: cset w0, hs
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i16 %x, 16882
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%1 = icmp ule i16 %0, -24837
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test16_3(i16 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test16_3:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: mov w8, #53200 ; =0xcfd0
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; CHECK-SD-NEXT: cmp w0, w8
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test16_3:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: mov w8, #29283 ; =0x7263
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; CHECK-GI-NEXT: mov w9, #16947 ; =0x4233
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; CHECK-GI-NEXT: add w8, w0, w8
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; CHECK-GI-NEXT: cmp w9, w8, uxth
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; CHECK-GI-NEXT: cset w0, ne
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i16 %x, 29283
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%1 = icmp ne i16 %0, 16947
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test16_4(i16 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test16_4:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: mov w8, #29985 ; =0x7521
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; CHECK-SD-NEXT: mov w9, #15676 ; =0x3d3c
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; CHECK-SD-NEXT: add w8, w0, w8
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; CHECK-SD-NEXT: cmp w9, w8, uxth
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; CHECK-SD-NEXT: cset w0, lo
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test16_4:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: mov w8, #29985 ; =0x7521
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; CHECK-GI-NEXT: mov w9, #15677 ; =0x3d3d
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; CHECK-GI-NEXT: add w8, w0, w8
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; CHECK-GI-NEXT: cmp w9, w8, uxth
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; CHECK-GI-NEXT: cset w0, ls
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i16 %x, -35551
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%1 = icmp uge i16 %0, 15677
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test16_5(i16 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test16_5:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: mov w8, #23282 ; =0x5af2
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; CHECK-SD-NEXT: cmp w0, w8
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; CHECK-SD-NEXT: cset w0, ne
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test16_5:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: mov w8, #-25214 ; =0xffff9d82
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; CHECK-GI-NEXT: mov w9, #63604 ; =0xf874
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; CHECK-GI-NEXT: add w8, w0, w8
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; CHECK-GI-NEXT: cmp w9, w8, uxth
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; CHECK-GI-NEXT: cset w0, ne
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i16 %x, -25214
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%1 = icmp ne i16 %0, -1932
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br i1 %1, label %ret_true, label %ret_false
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ret_false:
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ret i1 false
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ret_true:
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ret i1 true
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}
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define zeroext i1 @test16_6(i16 zeroext %x) align 2 {
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; CHECK-SD-LABEL: test16_6:
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; CHECK-SD: ; %bb.0: ; %entry
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; CHECK-SD-NEXT: mov w8, #-32194 ; =0xffff823e
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; CHECK-SD-NEXT: mov w9, #24320 ; =0x5f00
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; CHECK-SD-NEXT: add w8, w0, w8
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; CHECK-SD-NEXT: cmp w8, w9
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; CHECK-SD-NEXT: cset w0, hi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test16_6:
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; CHECK-GI: ; %bb.0: ; %entry
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; CHECK-GI-NEXT: mov w8, #-32194 ; =0xffff823e
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; CHECK-GI-NEXT: mov w9, #24321 ; =0x5f01
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; CHECK-GI-NEXT: add w8, w0, w8
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; CHECK-GI-NEXT: cmp w8, w9
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; CHECK-GI-NEXT: cset w0, hs
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; CHECK-GI-NEXT: ret
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entry:
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%0 = add i16 %x, -32194
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%1 = icmp uge i16 %0, -41215
|
|
br i1 %1, label %ret_true, label %ret_false
|
|
ret_false:
|
|
ret i1 false
|
|
ret_true:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @test16_7(i16 zeroext %x) align 2 {
|
|
; CHECK-SD-LABEL: test16_7:
|
|
; CHECK-SD: ; %bb.0: ; %entry
|
|
; CHECK-SD-NEXT: mov w8, #9272 ; =0x2438
|
|
; CHECK-SD-NEXT: mov w9, #22619 ; =0x585b
|
|
; CHECK-SD-NEXT: add w8, w0, w8
|
|
; CHECK-SD-NEXT: cmp w9, w8, uxth
|
|
; CHECK-SD-NEXT: cset w0, lo
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: test16_7:
|
|
; CHECK-GI: ; %bb.0: ; %entry
|
|
; CHECK-GI-NEXT: mov w8, #9272 ; =0x2438
|
|
; CHECK-GI-NEXT: mov w9, #22620 ; =0x585c
|
|
; CHECK-GI-NEXT: add w8, w0, w8
|
|
; CHECK-GI-NEXT: cmp w9, w8, uxth
|
|
; CHECK-GI-NEXT: cset w0, ls
|
|
; CHECK-GI-NEXT: ret
|
|
entry:
|
|
%0 = add i16 %x, 9272
|
|
%1 = icmp uge i16 %0, -42916
|
|
br i1 %1, label %ret_true, label %ret_false
|
|
ret_false:
|
|
ret i1 false
|
|
ret_true:
|
|
ret i1 true
|
|
}
|
|
|
|
define zeroext i1 @test16_8(i16 zeroext %x) align 2 {
|
|
; CHECK-SD-LABEL: test16_8:
|
|
; CHECK-SD: ; %bb.0: ; %entry
|
|
; CHECK-SD-NEXT: mov w8, #4919 ; =0x1337
|
|
; CHECK-SD-NEXT: cmp w0, w8
|
|
; CHECK-SD-NEXT: cset w0, ne
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: test16_8:
|
|
; CHECK-GI: ; %bb.0: ; %entry
|
|
; CHECK-GI-NEXT: mov w8, #6706 ; =0x1a32
|
|
; CHECK-GI-NEXT: add w9, w0, #1787
|
|
; CHECK-GI-NEXT: cmp w8, w9, uxth
|
|
; CHECK-GI-NEXT: cset w0, ne
|
|
; CHECK-GI-NEXT: ret
|
|
entry:
|
|
%0 = add i16 %x, -63749
|
|
%1 = icmp ne i16 %0, 6706
|
|
br i1 %1, label %ret_true, label %ret_false
|
|
ret_false:
|
|
ret i1 false
|
|
ret_true:
|
|
ret i1 true
|
|
}
|
|
|
|
define i64 @pr58109(i8 signext %0) {
|
|
; CHECK-SD-LABEL: pr58109:
|
|
; CHECK-SD: ; %bb.0:
|
|
; CHECK-SD-NEXT: add w8, w0, #1
|
|
; CHECK-SD-NEXT: and w8, w8, #0xff
|
|
; CHECK-SD-NEXT: subs w8, w8, #1
|
|
; CHECK-SD-NEXT: csel w0, wzr, w8, lo
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: pr58109:
|
|
; CHECK-GI: ; %bb.0:
|
|
; CHECK-GI-NEXT: add w8, w0, #1
|
|
; CHECK-GI-NEXT: and w8, w8, #0xff
|
|
; CHECK-GI-NEXT: sub w8, w8, #1
|
|
; CHECK-GI-NEXT: cmp w8, w8, uxtb
|
|
; CHECK-GI-NEXT: csel w8, wzr, w8, ne
|
|
; CHECK-GI-NEXT: and x0, x8, #0xff
|
|
; CHECK-GI-NEXT: ret
|
|
%2 = add i8 %0, 1
|
|
%3 = call i8 @llvm.usub.sat.i8(i8 %2, i8 1)
|
|
%4 = zext i8 %3 to i64
|
|
ret i64 %4
|
|
}
|
|
|
|
define i64 @pr58109b(i8 signext %0, i64 %a, i64 %b) {
|
|
; CHECK-SD-LABEL: pr58109b:
|
|
; CHECK-SD: ; %bb.0:
|
|
; CHECK-SD-NEXT: add w8, w0, #1
|
|
; CHECK-SD-NEXT: tst w8, #0xfe
|
|
; CHECK-SD-NEXT: csel x0, x1, x2, eq
|
|
; CHECK-SD-NEXT: ret
|
|
;
|
|
; CHECK-GI-LABEL: pr58109b:
|
|
; CHECK-GI: ; %bb.0:
|
|
; CHECK-GI-NEXT: add w8, w0, #1
|
|
; CHECK-GI-NEXT: and w8, w8, #0xff
|
|
; CHECK-GI-NEXT: cmp w8, #2
|
|
; CHECK-GI-NEXT: csel x0, x1, x2, lo
|
|
; CHECK-GI-NEXT: ret
|
|
%2 = add i8 %0, 1
|
|
%3 = icmp ult i8 %2, 2
|
|
%4 = select i1 %3, i64 %a, i64 %b
|
|
ret i64 %4
|
|
}
|
|
|
|
define i64 @test_2_selects(i8 zeroext %a) {
|
|
; CHECK-LABEL: test_2_selects:
|
|
; CHECK: ; %bb.0:
|
|
; CHECK-NEXT: add w9, w0, #24
|
|
; CHECK-NEXT: mov w8, #131
|
|
; CHECK-NEXT: and w9, w9, #0xff
|
|
; CHECK-NEXT: cmp w9, #81
|
|
; CHECK-NEXT: mov w9, #57
|
|
; CHECK-NEXT: csel x8, x8, xzr, lo
|
|
; CHECK-NEXT: csel x9, xzr, x9, eq
|
|
; CHECK-NEXT: add x0, x8, x9
|
|
; CHECK-NEXT: ret
|
|
%1 = add i8 %a, 24
|
|
%2 = zext i8 %1 to i64
|
|
%3 = icmp ult i8 %1, 81
|
|
%4 = select i1 %3, i64 131, i64 0
|
|
%5 = icmp eq i8 %1, 81
|
|
%6 = select i1 %5, i64 0, i64 57
|
|
%7 = add i64 %4, %6
|
|
ret i64 %7
|
|
}
|
|
|
|
declare i8 @llvm.usub.sat.i8(i8, i8) #0
|