146 lines
4.2 KiB
LLVM
146 lines
4.2 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s
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; FIXED WIDTH
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define i8 @ctz_v8i1(<8 x i1> %a) {
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; CHECK-LABEL: .LCPI0_0:
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .byte 7
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; CHECK-NEXT: .byte 6
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 1
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; CHECK-LABEL: ctz_v8i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.8b, v0.8b, #7
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: mov w9, #8 // =0x8
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: umaxv b0, v0.8b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: sub w0, w9, w8
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; CHECK-NEXT: ret
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%res = call i8 @llvm.experimental.cttz.elts.i8.v8i1(<8 x i1> %a, i1 0)
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ret i8 %res
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}
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define i32 @ctz_v16i1(<16 x i1> %a) {
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; CHECK-LABEL: .LCPI1_0:
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; CHECK-NEXT: .byte 16
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; CHECK-NEXT: .byte 15
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; CHECK-NEXT: .byte 14
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; CHECK-NEXT: .byte 13
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; CHECK-NEXT: .byte 12
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; CHECK-NEXT: .byte 11
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; CHECK-NEXT: .byte 10
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; CHECK-NEXT: .byte 9
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .byte 7
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; CHECK-NEXT: .byte 6
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 1
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; CHECK-LABEL: ctz_v16i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.16b, v0.16b, #7
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: mov w9, #16 // =0x10
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: cmlt v0.16b, v0.16b, #0
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: umaxv b0, v0.16b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: sub w8, w9, w8
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; CHECK-NEXT: and w0, w8, #0xff
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; CHECK-NEXT: ret
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%res = call i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1> %a, i1 0)
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ret i32 %res
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}
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define i16 @ctz_v4i32(<4 x i32> %a) {
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; CHECK-LABEL: .LCPI2_0:
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; CHECK-NEXT: .hword 4
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; CHECK-NEXT: .hword 3
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; CHECK-NEXT: .hword 2
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; CHECK-NEXT: .hword 1
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; CHECK-LABEL: ctz_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s
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; CHECK-NEXT: adrp x8, .LCPI2_0
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; CHECK-NEXT: mov w9, #4 // =0x4
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI2_0]
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: umaxv h0, v0.4h
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: sub w8, w9, w8
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; CHECK-NEXT: and w0, w8, #0xff
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; CHECK-NEXT: ret
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%res = call i16 @llvm.experimental.cttz.elts.i16.v4i32(<4 x i32> %a, i1 0)
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ret i16 %res
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}
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define i7 @ctz_i7_v8i1(<8 x i1> %a) {
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; CHECK-LABEL: .LCPI3_0:
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .byte 7
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; CHECK-NEXT: .byte 6
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 1
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; CHECK-LABEL: ctz_i7_v8i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.8b, v0.8b, #7
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; CHECK-NEXT: adrp x8, .LCPI3_0
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; CHECK-NEXT: mov w9, #8 // =0x8
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI3_0]
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; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: umaxv b0, v0.8b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: sub w0, w9, w8
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; CHECK-NEXT: ret
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%res = call i7 @llvm.experimental.cttz.elts.i7.v8i1(<8 x i1> %a, i1 0)
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ret i7 %res
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}
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; ZERO IS POISON
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define i8 @ctz_v8i1_poison(<8 x i1> %a) {
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; CHECK-LABEL: .LCPI4_0:
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; CHECK-NEXT: .byte 8
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; CHECK-NEXT: .byte 7
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; CHECK-NEXT: .byte 6
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; CHECK-NEXT: .byte 5
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; CHECK-NEXT: .byte 4
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; CHECK-NEXT: .byte 3
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; CHECK-NEXT: .byte 2
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; CHECK-NEXT: .byte 1
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; CHECK-LABEL: ctz_v8i1_poison:
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; CHECK: // %bb.0:
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; CHECK-NEXT: shl v0.8b, v0.8b, #7
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; CHECK-NEXT: adrp x8, .LCPI4_0
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; CHECK-NEXT: mov w9, #8 // =0x8
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; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_0]
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; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
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; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: umaxv b0, v0.8b
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; CHECK-NEXT: fmov w8, s0
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; CHECK-NEXT: sub w0, w9, w8
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; CHECK-NEXT: ret
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%res = call i8 @llvm.experimental.cttz.elts.i8.v8i1(<8 x i1> %a, i1 1)
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ret i8 %res
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}
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declare i8 @llvm.experimental.cttz.elts.i8.v8i1(<8 x i1>, i1)
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declare i7 @llvm.experimental.cttz.elts.i7.v8i1(<8 x i1>, i1)
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declare i32 @llvm.experimental.cttz.elts.i32.v16i1(<16 x i1>, i1)
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declare i16 @llvm.experimental.cttz.elts.i16.v4i32(<4 x i32>, i1)
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