bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AArch64/pr72777.ll
2025-02-14 19:21:04 +01:00

24 lines
759 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
define i64 @f(i64 %0, i64 %1) {
; CHECK-LABEL: f:
; CHECK: // %bb.0:
; CHECK-NEXT: orr x9, x1, #0x1
; CHECK-NEXT: add x10, x0, x0
; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000
; CHECK-NEXT: add x9, x9, x10
; CHECK-NEXT: lsl x10, x9, #1
; CHECK-NEXT: cmp x9, #0
; CHECK-NEXT: cinv x8, x8, ge
; CHECK-NEXT: cmp x9, x10, asr #1
; CHECK-NEXT: csel x0, x8, x10, ne
; CHECK-NEXT: ret
%3 = or i64 1, %1
%4 = add i64 %3, %0
%5 = add nsw i64 %4, %0
%6 = call i64 @llvm.sshl.sat.i64(i64 %5, i64 1)
ret i64 %6
}
declare i64 @llvm.sshl.sat.i64(i64, i64)