76 lines
3.1 KiB
LLVM
76 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; Ensure that a no-op 'and' get removed with vector splat of 1 or ptrue with proper constant
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define <vscale x 16 x i1> @fold_away_ptrue_and_ptrue() #0 {
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; CHECK-LABEL: fold_away_ptrue_and_ptrue:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
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%2 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%and = and <vscale x 16 x i1> %2, %1
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ret <vscale x 16 x i1> %and
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}
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define <vscale x 16 x i1> @fold_away_ptrue_and_splat_predicate() #0 {
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; CHECK-LABEL: fold_away_ptrue_and_splat_predicate:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ret
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entry:
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%ins = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
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%splat = shufflevector <vscale x 4 x i1> %ins, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
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%0 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %splat)
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%1 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%and = and <vscale x 16 x i1> %0, %1
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ret <vscale x 16 x i1> %and
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}
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; Ensure that one AND operation remain for inactive lanes zeroing with 2 x i1 type (llvm.aarch64.sve.convert.to.svbool.nxv2i1).
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define <vscale x 16 x i1> @fold_away_ptrue_and_convert_to() #0 {
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; CHECK-LABEL: fold_away_ptrue_and_convert_to:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ptrue p1.d
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; CHECK-NEXT: and p0.b, p1/z, p1.b, p0.b
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
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%1 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> %0)
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%2 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%3 = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %2)
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%4 = call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %3)
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%and = and <vscale x 16 x i1> %4, %1
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ret <vscale x 16 x i1> %and
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}
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define <vscale x 16 x i1> @fold_away_two_similar() #0 {
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; CHECK-LABEL: fold_away_two_similar:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: ret
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entry:
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%0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%1 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%and = and <vscale x 16 x i1> %0, %1
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ret <vscale x 16 x i1> %and
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}
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declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 immarg)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 immarg)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1>)
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attributes #0 = { "target-features"="+sve" }
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