bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s

---
name:            rcp_sqrt_test_f32
body:             |
  bb.0:
    liveins: $sgpr0

    ; GCN-LABEL: name: rcp_sqrt_test_f32
    ; GCN: liveins: $sgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; GCN-NEXT: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[COPY]]
    ; GCN-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FSQRT]](s32)
    ; GCN-NEXT: $vgpr0 = COPY [[INT]](s32)
    ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = G_FSQRT %0:_
    %3:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %2:_(s32)
    $vgpr0 = COPY %3:_(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0  

...

---
name:            contract_afn_rcp_contract_sqrt_test_f32
body:             |
  bb.0:
    liveins: $sgpr0

    ; GCN-LABEL: name: contract_afn_rcp_contract_sqrt_test_f32
    ; GCN: liveins: $sgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; GCN-NEXT: [[INT:%[0-9]+]]:_(s32) = contract afn G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)
    ; GCN-NEXT: $vgpr0 = COPY [[INT]](s32)
    ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = contract G_FSQRT %0:_
    %3:_(s32) = contract afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %2:_(s32)
    $vgpr0 = COPY %3:_(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0  

...

---
name:            sqrt_rcp_test_f32
body:             |
  bb.0:
    liveins: $sgpr0

    ; GCN-LABEL: name: sqrt_rcp_test_f32
    ; GCN: liveins: $sgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; GCN-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[COPY]](s32)
    ; GCN-NEXT: [[FSQRT:%[0-9]+]]:_(s32) = G_FSQRT [[INT]]
    ; GCN-NEXT: $vgpr0 = COPY [[FSQRT]](s32)
    ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $sgpr0
    %2:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0:_(s32)
    %3:_(s32) = G_FSQRT %2:_
    $vgpr0 = COPY %3:_(s32)
    SI_RETURN_TO_EPILOG implicit $vgpr0  

...

---
name:            afn_rcp_afn_amdgcn_sqrt_test_f32
body:             |
  bb.0:
    liveins: $sgpr0

    ; GCN-LABEL: name: afn_rcp_afn_amdgcn_sqrt_test_f32
    ; GCN: liveins: $sgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; GCN-NEXT: [[INT:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[COPY]](s32)
    ; GCN-NEXT: [[INT1:%[0-9]+]]:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](s32)
    ; GCN-NEXT: $vgpr0 = COPY [[INT1]](s32)
    ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %0:_(s32)
    %2:_(s32) = afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1:_(s32)
    $vgpr0 = COPY %2
    SI_RETURN_TO_EPILOG implicit $vgpr0  

...

---
name:            afn_contract_rcp_afn_contract_amdgcn_sqrt_test_f32
body:             |
  bb.0:
    liveins: $sgpr0

    ; GCN-LABEL: name: afn_contract_rcp_afn_contract_amdgcn_sqrt_test_f32
    ; GCN: liveins: $sgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; GCN-NEXT: [[INT:%[0-9]+]]:_(s32) = contract afn G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), [[COPY]](s32)
    ; GCN-NEXT: [[INT1:%[0-9]+]]:_(s32) = contract afn G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[INT]](s32)
    ; GCN-NEXT: $vgpr0 = COPY [[INT1]](s32)
    ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = afn contract G_INTRINSIC intrinsic(@llvm.amdgcn.sqrt), %0:_(s32)
    %2:_(s32) = afn contract G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1:_(s32)
    $vgpr0 = COPY %2
    SI_RETURN_TO_EPILOG implicit $vgpr0  

...

---
name:            rsq_test_f16
body:             |
  bb.0:
    liveins: $sgpr0

    ; GCN-LABEL: name: rsq_test_f16
    ; GCN: liveins: $sgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
    ; GCN-NEXT: %sqrt:_(s16) = G_FSQRT [[TRUNC]]
    ; GCN-NEXT: %one:_(s16) = contract G_FCONSTANT half 0xH3C00
    ; GCN-NEXT: %rsq:_(s16) = contract G_FDIV %one, %sqrt
    ; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
    ; GCN-NEXT: $vgpr0 = COPY %ext(s32)
    ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $sgpr0
    %1:_(s16) = G_TRUNC %0
    %sqrt:_(s16) = G_FSQRT %1:_
    %one:_(s16) = contract G_FCONSTANT half 1.0
    %rsq:_(s16) = contract G_FDIV %one, %sqrt
    %ext:_(s32) = G_ANYEXT %rsq
    $vgpr0 = COPY %ext
    SI_RETURN_TO_EPILOG implicit $vgpr0  

...

---
name:            neg_rsq_test_f16
body:             |
  bb.0:
    liveins: $sgpr0

    ; GCN-LABEL: name: neg_rsq_test_f16
    ; GCN: liveins: $sgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
    ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
    ; GCN-NEXT: %sqrt:_(s16) = G_FSQRT [[TRUNC]]
    ; GCN-NEXT: %one:_(s16) = contract G_FCONSTANT half 0xHBC00
    ; GCN-NEXT: %rsq:_(s16) = contract G_FDIV %one, %sqrt
    ; GCN-NEXT: %ext:_(s32) = G_ANYEXT %rsq(s16)
    ; GCN-NEXT: $vgpr0 = COPY %ext(s32)
    ; GCN-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
    %0:_(s32) = COPY $sgpr0
    %1:_(s16) = G_TRUNC %0
    %sqrt:_(s16) = G_FSQRT %1:_
    %one:_(s16) = contract G_FCONSTANT half -1.0
    %rsq:_(s16) = contract G_FDIV %one, %sqrt
    %ext:_(s32) = G_ANYEXT %rsq
    $vgpr0 = COPY %ext
    SI_RETURN_TO_EPILOG implicit $vgpr0  

...