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bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir
Sam Vervaeck 174b6f4d4e
Embed LLVM 18.1.8
2025-02-14 19:21:04 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1150 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1150 %s
---
name: fadd_f32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX1150-LABEL: name: fadd_f32
; GFX1150: liveins: $sgpr0, $sgpr1
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: %2:sreg_32 = nofpexcept S_ADD_F32 [[COPY]], [[COPY1]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_FADD %0, %1
$sgpr0 = COPY %2(s32)
...
---
name: fsub_f32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX1150-LABEL: name: fsub_f32
; GFX1150: liveins: $sgpr0, $sgpr1
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: %2:sreg_32 = nofpexcept S_SUB_F32 [[COPY]], [[COPY1]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_FSUB %0, %1
$sgpr0 = COPY %2(s32)
...
---
name: fmul_f32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX1150-LABEL: name: fmul_f32
; GFX1150: liveins: $sgpr0, $sgpr1
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: %2:sreg_32 = nofpexcept S_MUL_F32 [[COPY]], [[COPY1]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_FMUL %0, %1
$sgpr0 = COPY %2(s32)
...
---
name: fmin_f32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX1150-LABEL: name: fmin_f32
; GFX1150: liveins: $sgpr0, $sgpr1
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: %2:sreg_32 = nofpexcept S_MIN_F32 [[COPY]], [[COPY1]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_FMINNUM %0, %1
$sgpr0 = COPY %2(s32)
...
---
name: fmax_f32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX1150-LABEL: name: fmax_f32
; GFX1150: liveins: $sgpr0, $sgpr1
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: %2:sreg_32 = nofpexcept S_MAX_F32 [[COPY]], [[COPY1]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_FMAXNUM %0, %1
$sgpr0 = COPY %2(s32)
...
---
name: fadd_f16
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX1150-LABEL: name: fadd_f16
; GFX1150: liveins: $sgpr0, $sgpr1
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: %4:sreg_32 = nofpexcept S_ADD_F16 [[COPY]], [[COPY1]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %4
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0(s32)
%2:sgpr(s32) = COPY $sgpr1
%3:sgpr(s16) = G_TRUNC %2(s32)
%4:sgpr(s16) = G_FADD %1, %3
%5:sgpr(s32) = G_ANYEXT %4(s16)
$sgpr0 = COPY %5(s32)
...
---
name: fsub_f16
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX1150-LABEL: name: fsub_f16
; GFX1150: liveins: $sgpr0, $sgpr1
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: %4:sreg_32 = nofpexcept S_SUB_F16 [[COPY]], [[COPY1]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %4
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0(s32)
%2:sgpr(s32) = COPY $sgpr1
%3:sgpr(s16) = G_TRUNC %2(s32)
%4:sgpr(s16) = G_FSUB %1, %3
%5:sgpr(s32) = G_ANYEXT %4(s16)
$sgpr0 = COPY %5(s32)
...
---
name: fmul_f16
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX1150-LABEL: name: fmul_f16
; GFX1150: liveins: $sgpr0, $sgpr1
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: %4:sreg_32 = nofpexcept S_MUL_F16 [[COPY]], [[COPY1]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %4
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0(s32)
%2:sgpr(s32) = COPY $sgpr1
%3:sgpr(s16) = G_TRUNC %2(s32)
%4:sgpr(s16) = G_FMUL %1, %3
%5:sgpr(s32) = G_ANYEXT %4(s16)
$sgpr0 = COPY %5(s32)
...
---
name: fmin_f16
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX1150-LABEL: name: fmin_f16
; GFX1150: liveins: $sgpr0, $sgpr1
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: %4:sreg_32 = nofpexcept S_MIN_F16 [[COPY]], [[COPY1]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %4
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0(s32)
%2:sgpr(s32) = COPY $sgpr1
%3:sgpr(s16) = G_TRUNC %2(s32)
%4:sgpr(s16) = G_FMINNUM %1, %3
%5:sgpr(s32) = G_ANYEXT %4(s16)
$sgpr0 = COPY %5(s32)
...
---
name: fmax_f16
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX1150-LABEL: name: fmax_f16
; GFX1150: liveins: $sgpr0, $sgpr1
; GFX1150-NEXT: {{ $}}
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0(s32)
%2:sgpr(s32) = COPY $sgpr1
%3:sgpr(s16) = G_TRUNC %2(s32)
%4:sgpr(s16) = G_FMAXNUM %1, %3
%5:sgpr(s32) = G_ANYEXT %4(s16)
...
---
name: s_cvt_pkrtz_v2f16_f32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX1150-LABEL: name: s_cvt_pkrtz_v2f16_f32
; GFX1150: liveins: $sgpr0, $sgpr1
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: %2:sreg_32 = nofpexcept S_CVT_PK_RTZ_F16_F32 [[COPY]], [[COPY1]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0(s32), %1(s32)
$sgpr0 = COPY %2(<2 x s16>)
...
---
name: fmac_f32
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; GFX1150-LABEL: name: fmac_f32
; GFX1150: liveins: $sgpr0, $sgpr1, $sgpr2
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX1150-NEXT: %3:sreg_32 = nofpexcept S_FMAC_F32 [[COPY1]], [[COPY2]], [[COPY]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %3
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = COPY $sgpr2
%3:sgpr(s32) = G_FMA %1, %2, %0
$sgpr0 = COPY %3(s32)
...
---
name: fmac_f16
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; GFX1150-LABEL: name: fmac_f16
; GFX1150: liveins: $sgpr0, $sgpr1, $sgpr2
; GFX1150-NEXT: {{ $}}
; GFX1150-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX1150-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX1150-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX1150-NEXT: %6:sreg_32 = nofpexcept S_FMAC_F16 [[COPY1]], [[COPY2]], [[COPY]], implicit $mode
; GFX1150-NEXT: $sgpr0 = COPY %6
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0(s32)
%2:sgpr(s32) = COPY $sgpr1
%3:sgpr(s16) = G_TRUNC %2(s32)
%4:sgpr(s32) = COPY $sgpr2
%5:sgpr(s16) = G_TRUNC %4(s32)
%6:sgpr(s16) = G_FMA %3, %5, %1
%7:sgpr(s32) = G_ANYEXT %6(s16)
$sgpr0 = COPY %7(s32)
...
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