1737 lines
68 KiB
LLVM
1737 lines
68 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck -check-prefix=GFX6 %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck -check-prefix=GFX7 %s
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; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck -check-prefix=GFX12 %s
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; Test end to end matching of addressing modes when MUBUF is used for
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; global memory.
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define amdgpu_ps void @mubuf_store_sgpr_ptr(ptr addrspace(1) inreg %ptr) {
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; GFX6-LABEL: mubuf_store_sgpr_ptr:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_mov_b32 s0, s2
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; GFX6-NEXT: s_mov_b32 s1, s3
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; GFX6-NEXT: v_mov_b32_e32 v0, 0
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX7-LABEL: mubuf_store_sgpr_ptr:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_mov_b32 s0, s2
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; GFX7-NEXT: s_mov_b32 s1, s3
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; GFX7-NEXT: v_mov_b32_e32 v0, 0
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7-NEXT: s_endpgm
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;
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; GFX12-LABEL: mubuf_store_sgpr_ptr:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_mov_b32_e32 v0, 0
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; GFX12-NEXT: global_store_b32 v0, v0, s[2:3]
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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store i32 0, ptr addrspace(1) %ptr
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ret void
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}
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define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4095(ptr addrspace(1) inreg %ptr) {
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; GFX6-LABEL: mubuf_store_sgpr_ptr_offset4095:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_mov_b32 s0, s2
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; GFX6-NEXT: s_mov_b32 s1, s3
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; GFX6-NEXT: v_mov_b32_e32 v0, 0
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
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; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], s4
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; GFX6-NEXT: s_endpgm
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;
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; GFX7-LABEL: mubuf_store_sgpr_ptr_offset4095:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_mov_b32 s0, s2
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; GFX7-NEXT: s_mov_b32 s1, s3
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; GFX7-NEXT: v_mov_b32_e32 v0, 0
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], s4
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; GFX7-NEXT: s_endpgm
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;
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; GFX12-LABEL: mubuf_store_sgpr_ptr_offset4095:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_mov_b32_e32 v0, 0
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; GFX12-NEXT: global_store_b32 v0, v0, s[2:3] offset:16380
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4095
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store i32 0, ptr addrspace(1) %gep
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ret void
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}
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define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4294967296(ptr addrspace(1) inreg %ptr) {
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; GFX6-LABEL: mubuf_store_sgpr_ptr_offset4294967296:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_mov_b32 s4, 0
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; GFX6-NEXT: s_mov_b32 s5, 4
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; GFX6-NEXT: v_mov_b32_e32 v0, s4
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; GFX6-NEXT: s_mov_b32 s0, s2
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; GFX6-NEXT: s_mov_b32 s1, s3
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; GFX6-NEXT: v_mov_b32_e32 v2, 0
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, s4
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; GFX6-NEXT: v_mov_b32_e32 v1, s5
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; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX6-NEXT: s_endpgm
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;
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; GFX7-LABEL: mubuf_store_sgpr_ptr_offset4294967296:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_mov_b32 s4, 0
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; GFX7-NEXT: s_mov_b32 s5, 4
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; GFX7-NEXT: v_mov_b32_e32 v0, s4
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; GFX7-NEXT: s_mov_b32 s0, s2
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; GFX7-NEXT: s_mov_b32 s1, s3
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; GFX7-NEXT: v_mov_b32_e32 v2, 0
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_mov_b32 s2, s4
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; GFX7-NEXT: v_mov_b32_e32 v1, s5
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; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX7-NEXT: s_endpgm
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;
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; GFX12-LABEL: mubuf_store_sgpr_ptr_offset4294967296:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_add_co_u32 s0, s2, 0
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; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967296
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store i32 0, ptr addrspace(1) %gep
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ret void
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}
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define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4294967297(ptr addrspace(1) inreg %ptr) {
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; GFX6-LABEL: mubuf_store_sgpr_ptr_offset4294967297:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_mov_b32 s4, 4
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; GFX6-NEXT: s_mov_b32 s5, s4
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; GFX6-NEXT: v_mov_b32_e32 v0, s4
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; GFX6-NEXT: s_mov_b32 s0, s2
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; GFX6-NEXT: s_mov_b32 s1, s3
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; GFX6-NEXT: s_mov_b32 s2, 0
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; GFX6-NEXT: v_mov_b32_e32 v2, 0
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: v_mov_b32_e32 v1, s5
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; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX6-NEXT: s_endpgm
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;
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; GFX7-LABEL: mubuf_store_sgpr_ptr_offset4294967297:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_mov_b32 s4, 4
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; GFX7-NEXT: s_mov_b32 s5, s4
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; GFX7-NEXT: v_mov_b32_e32 v0, s4
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; GFX7-NEXT: s_mov_b32 s0, s2
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; GFX7-NEXT: s_mov_b32 s1, s3
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; GFX7-NEXT: s_mov_b32 s2, 0
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; GFX7-NEXT: v_mov_b32_e32 v2, 0
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: v_mov_b32_e32 v1, s5
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; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX7-NEXT: s_endpgm
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;
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; GFX12-LABEL: mubuf_store_sgpr_ptr_offset4294967297:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_add_co_u32 s0, s2, 4
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; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967297
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store i32 0, ptr addrspace(1) %gep
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ret void
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}
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define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4096(ptr addrspace(1) inreg %ptr) {
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; GFX6-LABEL: mubuf_store_sgpr_ptr_offset4096:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_mov_b32 s0, s2
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; GFX6-NEXT: s_mov_b32 s1, s3
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; GFX6-NEXT: v_mov_b32_e32 v0, 0
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_movk_i32 s4, 0x4000
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; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], s4
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; GFX6-NEXT: s_endpgm
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;
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; GFX7-LABEL: mubuf_store_sgpr_ptr_offset4096:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_mov_b32 s0, s2
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; GFX7-NEXT: s_mov_b32 s1, s3
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; GFX7-NEXT: v_mov_b32_e32 v0, 0
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_movk_i32 s4, 0x4000
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], s4
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; GFX7-NEXT: s_endpgm
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;
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; GFX12-LABEL: mubuf_store_sgpr_ptr_offset4096:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_mov_b32_e32 v0, 0
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; GFX12-NEXT: global_store_b32 v0, v0, s[2:3] offset:16384
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4096
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store i32 0, ptr addrspace(1) %gep
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ret void
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}
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define amdgpu_ps void @mubuf_store_vgpr_ptr_offset4095(ptr addrspace(1) %ptr) {
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; GFX6-LABEL: mubuf_store_vgpr_ptr_offset4095:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_mov_b32 s2, 0
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; GFX6-NEXT: v_mov_b32_e32 v2, 0
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b64 s[0:1], 0
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; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
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; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], s4 addr64
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; GFX6-NEXT: s_endpgm
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;
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; GFX7-LABEL: mubuf_store_vgpr_ptr_offset4095:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_mov_b32 s2, 0
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; GFX7-NEXT: v_mov_b32_e32 v2, 0
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_mov_b64 s[0:1], 0
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; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
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; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], s4 addr64
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; GFX7-NEXT: s_endpgm
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;
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; GFX12-LABEL: mubuf_store_vgpr_ptr_offset4095:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_mov_b32_e32 v2, 0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off offset:16380
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4095
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store i32 0, ptr addrspace(1) %gep
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ret void
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}
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define amdgpu_ps void @mubuf_store_vgpr_ptr_offset4294967296(ptr addrspace(1) %ptr) {
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; GFX6-LABEL: mubuf_store_vgpr_ptr_offset4294967296:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_mov_b32 s0, 0
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; GFX6-NEXT: s_mov_b32 s1, 4
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; GFX6-NEXT: v_mov_b32_e32 v2, 0
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, s0
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; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX6-NEXT: s_endpgm
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;
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; GFX7-LABEL: mubuf_store_vgpr_ptr_offset4294967296:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_mov_b32 s0, 0
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; GFX7-NEXT: s_mov_b32 s1, 4
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; GFX7-NEXT: v_mov_b32_e32 v2, 0
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_mov_b32 s2, s0
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; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX7-NEXT: s_endpgm
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;
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; GFX12-LABEL: mubuf_store_vgpr_ptr_offset4294967296:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_mov_b32 s0, 0
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; GFX12-NEXT: s_mov_b32 s1, 4
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
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; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
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; GFX12-NEXT: v_mov_b32_e32 v2, 0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
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%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967296
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store i32 0, ptr addrspace(1) %gep
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ret void
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}
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define amdgpu_ps void @mubuf_store_vgpr_ptr_offset4294967297(ptr addrspace(1) %ptr) {
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; GFX6-LABEL: mubuf_store_vgpr_ptr_offset4294967297:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_mov_b32 s0, 4
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; GFX6-NEXT: s_mov_b32 s1, s0
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; GFX6-NEXT: s_mov_b32 s2, 0
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; GFX6-NEXT: v_mov_b32_e32 v2, 0
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX6-NEXT: s_endpgm
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;
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; GFX7-LABEL: mubuf_store_vgpr_ptr_offset4294967297:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_mov_b32 s0, 4
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; GFX7-NEXT: s_mov_b32 s1, s0
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; GFX7-NEXT: s_mov_b32 s2, 0
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; GFX7-NEXT: v_mov_b32_e32 v2, 0
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
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; GFX7-NEXT: s_endpgm
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;
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; GFX12-LABEL: mubuf_store_vgpr_ptr_offset4294967297:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_mov_b32 s0, 4
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX12-NEXT: s_mov_b32 s1, s0
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; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
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; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
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; GFX12-NEXT: v_mov_b32_e32 v2, 0
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; GFX12-NEXT: global_store_b32 v[0:1], v2, off
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; GFX12-NEXT: s_nop 0
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; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX12-NEXT: s_endpgm
|
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%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967297
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store i32 0, ptr addrspace(1) %gep
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ret void
|
|
}
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define amdgpu_ps void @mubuf_store_vgpr_ptr_offset4096(ptr addrspace(1) %ptr) {
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; GFX6-LABEL: mubuf_store_vgpr_ptr_offset4096:
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|
; GFX6: ; %bb.0:
|
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; GFX6-NEXT: s_mov_b32 s2, 0
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; GFX6-NEXT: v_mov_b32_e32 v2, 0
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b64 s[0:1], 0
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x4000
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], s4 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX7-LABEL: mubuf_store_vgpr_ptr_offset4096:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_mov_b64 s[0:1], 0
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x4000
|
|
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], s4 addr64
|
|
; GFX7-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: mubuf_store_vgpr_ptr_offset4096:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v2, off offset:16384
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4096
|
|
store i32 0, ptr addrspace(1) %gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @mubuf_store_sgpr_ptr_sgpr_offset(ptr addrspace(1) inreg %ptr, i32 inreg %soffset) {
|
|
; GFX6-LABEL: mubuf_store_sgpr_ptr_sgpr_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_ashr_i32 s5, s4, 31
|
|
; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, s5
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX7-LABEL: mubuf_store_sgpr_ptr_sgpr_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_ashr_i32 s5, s4, 31
|
|
; GFX7-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: v_mov_b32_e32 v1, s5
|
|
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX7-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: mubuf_store_sgpr_ptr_sgpr_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_ashr_i32 s5, s4, 31
|
|
; GFX12-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX12-NEXT: s_lshl_b64 s[0:1], s[4:5], 2
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX12-NEXT: s_add_co_u32 s0, s2, s0
|
|
; GFX12-NEXT: s_add_co_ci_u32 s1, s3, s1
|
|
; GFX12-NEXT: global_store_b32 v0, v0, s[0:1]
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %soffset
|
|
store i32 0, ptr addrspace(1) %gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset(ptr addrspace(1) %ptr, i32 inreg %soffset) {
|
|
; GFX6-LABEL: mubuf_store_vgpr_ptr_sgpr_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX6-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX7-LABEL: mubuf_store_vgpr_ptr_sgpr_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX7-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX7-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: mubuf_store_vgpr_ptr_sgpr_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
|
; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %soffset
|
|
store i32 0, ptr addrspace(1) %gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset_offset256(ptr addrspace(1) %ptr, i32 inreg %soffset) {
|
|
; GFX6-LABEL: mubuf_store_vgpr_ptr_sgpr_offset_offset256:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX6-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 offset:1024
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX7-LABEL: mubuf_store_vgpr_ptr_sgpr_offset_offset256:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX7-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 offset:1024
|
|
; GFX7-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: mubuf_store_vgpr_ptr_sgpr_offset_offset256:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
|
; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v2, off offset:1024
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%gep0 = getelementptr i32, ptr addrspace(1) %ptr, i32 %soffset
|
|
%gep1 = getelementptr i32, ptr addrspace(1) %gep0, i32 256
|
|
store i32 0, ptr addrspace(1) %gep1
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset256_offset(ptr addrspace(1) %ptr, i32 inreg %soffset) {
|
|
; GFX6-LABEL: mubuf_store_vgpr_ptr_sgpr_offset256_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX6-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 offset:1024
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX7-LABEL: mubuf_store_vgpr_ptr_sgpr_offset256_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX7-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 offset:1024
|
|
; GFX7-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: mubuf_store_vgpr_ptr_sgpr_offset256_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
|
; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v2, off offset:1024
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%gep0 = getelementptr i32, ptr addrspace(1) %ptr, i32 256
|
|
%gep1 = getelementptr i32, ptr addrspace(1) %gep0, i32 %soffset
|
|
store i32 0, ptr addrspace(1) %gep1
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @mubuf_store_sgpr_ptr_vgpr_offset(ptr addrspace(1) inreg %ptr, i32 %voffset) {
|
|
; GFX6-LABEL: mubuf_store_sgpr_ptr_vgpr_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX7-LABEL: mubuf_store_sgpr_ptr_vgpr_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
|
|
; GFX7-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: mubuf_store_sgpr_ptr_vgpr_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %voffset
|
|
store i32 0, ptr addrspace(1) %gep
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @mubuf_store_sgpr_ptr_vgpr_offset_offset4095(ptr addrspace(1) inreg %ptr, i32 %voffset) {
|
|
; GFX6-LABEL: mubuf_store_sgpr_ptr_vgpr_offset_offset4095:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], s4 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX7-LABEL: mubuf_store_sgpr_ptr_vgpr_offset_offset4095:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], s4 addr64
|
|
; GFX7-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: mubuf_store_sgpr_ptr_vgpr_offset_offset4095:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v2, off offset:16380
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%gep0 = getelementptr i32, ptr addrspace(1) %ptr, i32 %voffset
|
|
%gep1 = getelementptr i32, ptr addrspace(1) %gep0, i32 4095
|
|
store i32 0, ptr addrspace(1) %gep1
|
|
ret void
|
|
}
|
|
define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4095_vgpr_offset(ptr addrspace(1) inreg %ptr, i32 %voffset) {
|
|
; GFX6-LABEL: mubuf_store_sgpr_ptr_offset4095_vgpr_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[0:3], s4 addr64
|
|
; GFX6-NEXT: s_endpgm
|
|
;
|
|
; GFX7-LABEL: mubuf_store_sgpr_ptr_offset4095_vgpr_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX7-NEXT: buffer_store_dword v2, v[0:1], s[0:3], s4 addr64
|
|
; GFX7-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: mubuf_store_sgpr_ptr_offset4095_vgpr_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, 0
|
|
; GFX12-NEXT: global_store_b32 v[0:1], v2, off offset:16380
|
|
; GFX12-NEXT: s_nop 0
|
|
; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX12-NEXT: s_endpgm
|
|
%gep0 = getelementptr i32, ptr addrspace(1) %ptr, i32 4095
|
|
%gep1 = getelementptr i32, ptr addrspace(1) %gep0, i32 %voffset
|
|
store i32 0, ptr addrspace(1) %gep1
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_sgpr_ptr(ptr addrspace(1) inreg %ptr) {
|
|
; GFX6-LABEL: mubuf_load_sgpr_ptr:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, -1
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_sgpr_ptr:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, -1
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_sgpr_ptr:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%val = load volatile float, ptr addrspace(1) %ptr
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4095(ptr addrspace(1) inreg %ptr) {
|
|
; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4095:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, -1
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], s4 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4095:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, -1
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s4 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_sgpr_ptr_offset4095:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:16380 scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr float, ptr addrspace(1) %ptr, i64 4095
|
|
%val = load volatile float, ptr addrspace(1) %gep
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4294967296(ptr addrspace(1) inreg %ptr) {
|
|
; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4294967296:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s4, 0
|
|
; GFX6-NEXT: s_mov_b32 s5, 4
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, s4
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, s5
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4294967296:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s4, 0
|
|
; GFX7-NEXT: s_mov_b32 s5, 4
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_mov_b32 s2, s4
|
|
; GFX7-NEXT: v_mov_b32_e32 v1, s5
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_sgpr_ptr_offset4294967296:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_add_co_u32 s0, s2, 0
|
|
; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr float, ptr addrspace(1) %ptr, i64 4294967296
|
|
%val = load volatile float, ptr addrspace(1) %gep
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4294967297(ptr addrspace(1) inreg %ptr) {
|
|
; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4294967297:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s4, 4
|
|
; GFX6-NEXT: s_mov_b32 s5, s4
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, s5
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4294967297:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s4, 4
|
|
; GFX7-NEXT: s_mov_b32 s5, s4
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: v_mov_b32_e32 v1, s5
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_sgpr_ptr_offset4294967297:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_add_co_u32 s0, s2, 4
|
|
; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr float, ptr addrspace(1) %ptr, i64 4294967297
|
|
%val = load volatile float, ptr addrspace(1) %gep
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4096(ptr addrspace(1) inreg %ptr) {
|
|
; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4096:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, -1
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x4000
|
|
; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], s4 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4096:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, -1
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x4000
|
|
; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s4 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_sgpr_ptr_offset4096:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:16384 scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr float, ptr addrspace(1) %ptr, i64 4096
|
|
%val = load volatile float, ptr addrspace(1) %gep
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4095(ptr addrspace(1) %ptr) {
|
|
; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4095:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b64 s[0:1], 0
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4095:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_mov_b64 s[0:1], 0
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_vgpr_ptr_offset4095:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off offset:16380 scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr float, ptr addrspace(1) %ptr, i64 4095
|
|
%val = load volatile float, ptr addrspace(1) %gep
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4294967296(ptr addrspace(1) %ptr) {
|
|
; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4294967296:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s0, 0
|
|
; GFX6-NEXT: s_mov_b32 s1, 4
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, s0
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4294967296:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s0, 0
|
|
; GFX7-NEXT: s_mov_b32 s1, 4
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_mov_b32 s2, s0
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_vgpr_ptr_offset4294967296:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_mov_b32 s0, 0
|
|
; GFX12-NEXT: s_mov_b32 s1, 4
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr float, ptr addrspace(1) %ptr, i64 4294967296
|
|
%val = load volatile float, ptr addrspace(1) %gep
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4294967297(ptr addrspace(1) %ptr) {
|
|
; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4294967297:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s0, 4
|
|
; GFX6-NEXT: s_mov_b32 s1, s0
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4294967297:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s0, 4
|
|
; GFX7-NEXT: s_mov_b32 s1, s0
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_vgpr_ptr_offset4294967297:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_mov_b32 s0, 4
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
|
; GFX12-NEXT: s_mov_b32 s1, s0
|
|
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr float, ptr addrspace(1) %ptr, i64 4294967297
|
|
%val = load volatile float, ptr addrspace(1) %gep
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4096(ptr addrspace(1) %ptr) {
|
|
; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4096:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b64 s[0:1], 0
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x4000
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4096:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_mov_b64 s[0:1], 0
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x4000
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_vgpr_ptr_offset4096:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off offset:16384 scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr float, ptr addrspace(1) %ptr, i64 4096
|
|
%val = load volatile float, ptr addrspace(1) %gep
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_sgpr_ptr_sgpr_offset(ptr addrspace(1) inreg %ptr, i32 inreg %soffset) {
|
|
; GFX6-LABEL: mubuf_load_sgpr_ptr_sgpr_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_ashr_i32 s5, s4, 31
|
|
; GFX6-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, s5
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_sgpr_ptr_sgpr_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_ashr_i32 s5, s4, 31
|
|
; GFX7-NEXT: s_lshl_b64 s[4:5], s[4:5], 2
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, s4
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: v_mov_b32_e32 v1, s5
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_sgpr_ptr_sgpr_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_ashr_i32 s5, s4, 31
|
|
; GFX12-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX12-NEXT: s_lshl_b64 s[0:1], s[4:5], 2
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX12-NEXT: s_add_co_u32 s0, s2, s0
|
|
; GFX12-NEXT: s_add_co_ci_u32 s1, s3, s1
|
|
; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr float, ptr addrspace(1) %ptr, i32 %soffset
|
|
%val = load volatile float, ptr addrspace(1) %gep
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset(ptr addrspace(1) %ptr, i32 inreg %soffset) {
|
|
; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX6-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX7-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_vgpr_ptr_sgpr_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
|
; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr float, ptr addrspace(1) %ptr, i32 %soffset
|
|
%val = load volatile float, ptr addrspace(1) %gep
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset_offset256(ptr addrspace(1) %ptr, i32 inreg %soffset) {
|
|
; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX6-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX7-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
|
; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off offset:1024 scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep0 = getelementptr float, ptr addrspace(1) %ptr, i32 %soffset
|
|
%gep1 = getelementptr float, ptr addrspace(1) %gep0, i32 256
|
|
%val = load volatile float, ptr addrspace(1) %gep1
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset256_offset(ptr addrspace(1) %ptr, i32 inreg %soffset) {
|
|
; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX6-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX7-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_ashr_i32 s3, s2, 31
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
|
; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2
|
|
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off offset:1024 scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep0 = getelementptr float, ptr addrspace(1) %ptr, i64 256
|
|
%gep1 = getelementptr float, ptr addrspace(1) %gep0, i32 %soffset
|
|
%val = load volatile float, ptr addrspace(1) %gep1
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset(ptr addrspace(1) inreg %ptr, i32 %voffset) {
|
|
; GFX6-LABEL: mubuf_load_sgpr_ptr_vgpr_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_sgpr_ptr_vgpr_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_sgpr_ptr_vgpr_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr float, ptr addrspace(1) %ptr, i32 %voffset
|
|
%val = load volatile float, ptr addrspace(1) %gep
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset_offset4095(ptr addrspace(1) inreg %ptr, i32 %voffset) {
|
|
; GFX6-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off offset:16380 scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep0 = getelementptr float, ptr addrspace(1) %ptr, i32 %voffset
|
|
%gep1 = getelementptr float, ptr addrspace(1) %gep0, i64 4095
|
|
%val = load volatile float, ptr addrspace(1) %gep1
|
|
ret float %val
|
|
}
|
|
define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4095_vgpr_offset(ptr addrspace(1) inreg %ptr, i32 %voffset) {
|
|
; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
|
|
; GFX12-NEXT: global_load_b32 v0, v[0:1], off offset:16380 scope:SCOPE_SYS
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep0 = getelementptr float, ptr addrspace(1) %ptr, i64 4095
|
|
%gep1 = getelementptr float, ptr addrspace(1) %gep0, i32 %voffset
|
|
%val = load volatile float, ptr addrspace(1) %gep1
|
|
ret float %val
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_offset4095(ptr addrspace(1) inreg %ptr) {
|
|
; GFX6-LABEL: mubuf_atomicrmw_sgpr_ptr_offset4095:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, 2
|
|
; GFX6-NEXT: s_mov_b32 s2, -1
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX6-NEXT: buffer_atomic_add v0, off, s[0:3], s4 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: buffer_wbinvl1
|
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_atomicrmw_sgpr_ptr_offset4095:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, 2
|
|
; GFX7-NEXT: s_mov_b32 s2, -1
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX7-NEXT: buffer_atomic_add v0, off, s[0:3], s4 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: buffer_wbinvl1
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_atomicrmw_sgpr_ptr_offset4095:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_dual_mov_b32 v0, 2 :: v_dual_mov_b32 v1, 0
|
|
; GFX12-NEXT: global_atomic_add_u32 v0, v1, v0, s[2:3] offset:16380 th:TH_ATOMIC_RETURN
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: global_inv scope:SCOPE_DEV
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4095
|
|
%result = atomicrmw add ptr addrspace(1) %gep, i32 2 syncscope("agent") seq_cst
|
|
%cast = bitcast i32 %result to float
|
|
ret float %cast
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_offset4294967296(ptr addrspace(1) inreg %ptr) {
|
|
; GFX6-LABEL: mubuf_atomicrmw_sgpr_ptr_offset4294967296:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s4, 0
|
|
; GFX6-NEXT: s_mov_b32 s5, 4
|
|
; GFX6-NEXT: v_mov_b32_e32 v1, s4
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, 2
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, s4
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, s5
|
|
; GFX6-NEXT: buffer_atomic_add v0, v[1:2], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: buffer_wbinvl1
|
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_atomicrmw_sgpr_ptr_offset4294967296:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s4, 0
|
|
; GFX7-NEXT: s_mov_b32 s5, 4
|
|
; GFX7-NEXT: v_mov_b32_e32 v1, s4
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, 2
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_mov_b32 s2, s4
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, s5
|
|
; GFX7-NEXT: buffer_atomic_add v0, v[1:2], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: buffer_wbinvl1
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_atomicrmw_sgpr_ptr_offset4294967296:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_add_co_u32 s0, s2, 0
|
|
; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, 2
|
|
; GFX12-NEXT: global_atomic_add_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: global_inv scope:SCOPE_DEV
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967296
|
|
%result = atomicrmw add ptr addrspace(1) %gep, i32 2 syncscope("agent") seq_cst
|
|
%cast = bitcast i32 %result to float
|
|
ret float %cast
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_atomicrmw_vgpr_ptr_offset4095(ptr addrspace(1) %ptr) {
|
|
; GFX6-LABEL: mubuf_atomicrmw_vgpr_ptr_offset4095:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 2
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b64 s[0:1], 0
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX6-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: buffer_wbinvl1
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, v2
|
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_atomicrmw_vgpr_ptr_offset4095:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, 2
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_mov_b64 s[0:1], 0
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX7-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: buffer_wbinvl1
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, v2
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_atomicrmw_vgpr_ptr_offset4095:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, 2
|
|
; GFX12-NEXT: global_atomic_add_u32 v0, v[0:1], v2, off offset:16380 th:TH_ATOMIC_RETURN
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: global_inv scope:SCOPE_DEV
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4095
|
|
%result = atomicrmw add ptr addrspace(1) %gep, i32 2 syncscope("agent") seq_cst
|
|
%cast = bitcast i32 %result to float
|
|
ret float %cast
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_atomicrmw_vgpr_ptr_offset4294967296(ptr addrspace(1) %ptr) {
|
|
; GFX6-LABEL: mubuf_atomicrmw_vgpr_ptr_offset4294967296:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s0, 0
|
|
; GFX6-NEXT: s_mov_b32 s1, 4
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 2
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, s0
|
|
; GFX6-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: buffer_wbinvl1
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, v2
|
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_atomicrmw_vgpr_ptr_offset4294967296:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s0, 0
|
|
; GFX7-NEXT: s_mov_b32 s1, 4
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, 2
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_mov_b32 s2, s0
|
|
; GFX7-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: buffer_wbinvl1
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, v2
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_atomicrmw_vgpr_ptr_offset4294967296:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_mov_b32 s0, 0
|
|
; GFX12-NEXT: s_mov_b32 s1, 4
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, 2
|
|
; GFX12-NEXT: global_atomic_add_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: global_inv scope:SCOPE_DEV
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967296
|
|
%result = atomicrmw add ptr addrspace(1) %gep, i32 2 syncscope("agent") seq_cst
|
|
%cast = bitcast i32 %result to float
|
|
ret float %cast
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_vgpr_offset(ptr addrspace(1) inreg %ptr, i32 %voffset) {
|
|
; GFX6-LABEL: mubuf_atomicrmw_sgpr_ptr_vgpr_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, 2
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: buffer_wbinvl1
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, v2
|
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_atomicrmw_sgpr_ptr_vgpr_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, 2
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: buffer_wbinvl1
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, v2
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_atomicrmw_sgpr_ptr_vgpr_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
|
|
; GFX12-NEXT: v_mov_b32_e32 v4, 2
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
|
|
; GFX12-NEXT: global_atomic_add_u32 v0, v[0:1], v4, off th:TH_ATOMIC_RETURN
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: global_inv scope:SCOPE_DEV
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %voffset
|
|
%result = atomicrmw add ptr addrspace(1) %gep, i32 2 syncscope("agent") seq_cst
|
|
%cast = bitcast i32 %result to float
|
|
ret float %cast
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_offset4095(ptr addrspace(1) inreg %ptr, i32 %old, i32 %in) {
|
|
; GFX6-LABEL: mubuf_cmpxchg_sgpr_ptr_offset4095:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, v0
|
|
; GFX6-NEXT: s_mov_b32 s2, -1
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX6-NEXT: buffer_atomic_cmpswap v[1:2], off, s[0:3], s4 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: buffer_wbinvl1
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, v1
|
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_cmpxchg_sgpr_ptr_offset4095:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, v0
|
|
; GFX7-NEXT: s_mov_b32 s2, -1
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX7-NEXT: buffer_atomic_cmpswap v[1:2], off, s[0:3], s4 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: buffer_wbinvl1
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, v1
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_cmpxchg_sgpr_ptr_offset4095:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, v0
|
|
; GFX12-NEXT: v_mov_b32_e32 v0, 0
|
|
; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v0, v[1:2], s[2:3] offset:16380 th:TH_ATOMIC_RETURN
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: global_inv scope:SCOPE_DEV
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4095
|
|
%result.struct = cmpxchg ptr addrspace(1) %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst
|
|
%result = extractvalue { i32, i1 } %result.struct, 0
|
|
%cast = bitcast i32 %result to float
|
|
ret float %cast
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_offset4294967296(ptr addrspace(1) inreg %ptr, i32 %old, i32 %in) {
|
|
; GFX6-LABEL: mubuf_cmpxchg_sgpr_ptr_offset4294967296:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s4, 0
|
|
; GFX6-NEXT: s_mov_b32 s5, 4
|
|
; GFX6-NEXT: v_mov_b32_e32 v3, s4
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: v_mov_b32_e32 v2, v0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, s4
|
|
; GFX6-NEXT: v_mov_b32_e32 v4, s5
|
|
; GFX6-NEXT: buffer_atomic_cmpswap v[1:2], v[3:4], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: buffer_wbinvl1
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, v1
|
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_cmpxchg_sgpr_ptr_offset4294967296:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s4, 0
|
|
; GFX7-NEXT: s_mov_b32 s5, 4
|
|
; GFX7-NEXT: v_mov_b32_e32 v3, s4
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: v_mov_b32_e32 v2, v0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_mov_b32 s2, s4
|
|
; GFX7-NEXT: v_mov_b32_e32 v4, s5
|
|
; GFX7-NEXT: buffer_atomic_cmpswap v[1:2], v[3:4], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: buffer_wbinvl1
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, v1
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_cmpxchg_sgpr_ptr_offset4294967296:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_add_co_u32 s0, s2, 0
|
|
; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4
|
|
; GFX12-NEXT: v_mov_b32_e32 v2, v0
|
|
; GFX12-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
|
|
; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[3:4], v[1:2], off th:TH_ATOMIC_RETURN
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: global_inv scope:SCOPE_DEV
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967296
|
|
%result.struct = cmpxchg ptr addrspace(1) %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst
|
|
%result = extractvalue { i32, i1 } %result.struct, 0
|
|
%cast = bitcast i32 %result to float
|
|
ret float %cast
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_cmpxchg_vgpr_ptr_offset4095(ptr addrspace(1) %ptr, i32 %old, i32 %in) {
|
|
; GFX6-LABEL: mubuf_cmpxchg_vgpr_ptr_offset4095:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: v_mov_b32_e32 v4, v2
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b64 s[0:1], 0
|
|
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX6-NEXT: buffer_atomic_cmpswap v[3:4], v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: buffer_wbinvl1
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, v3
|
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_cmpxchg_vgpr_ptr_offset4095:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: v_mov_b32_e32 v4, v2
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_mov_b64 s[0:1], 0
|
|
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
|
|
; GFX7-NEXT: buffer_atomic_cmpswap v[3:4], v[0:1], s[0:3], s4 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: buffer_wbinvl1
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, v3
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_cmpxchg_vgpr_ptr_offset4095:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_mov_b32_e32 v4, v2
|
|
; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[0:1], v[3:4], off offset:16380 th:TH_ATOMIC_RETURN
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: global_inv scope:SCOPE_DEV
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4095
|
|
%result.struct = cmpxchg ptr addrspace(1) %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst
|
|
%result = extractvalue { i32, i1 } %result.struct, 0
|
|
%cast = bitcast i32 %result to float
|
|
ret float %cast
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_cmpxchg_vgpr_ptr_offset4294967296(ptr addrspace(1) %ptr, i32 %old, i32 %in) {
|
|
; GFX6-LABEL: mubuf_cmpxchg_vgpr_ptr_offset4294967296:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: s_mov_b32 s0, 0
|
|
; GFX6-NEXT: v_mov_b32_e32 v4, v2
|
|
; GFX6-NEXT: s_mov_b32 s1, 4
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: s_mov_b32 s2, s0
|
|
; GFX6-NEXT: buffer_atomic_cmpswap v[3:4], v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: buffer_wbinvl1
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, v3
|
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_cmpxchg_vgpr_ptr_offset4294967296:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: s_mov_b32 s0, 0
|
|
; GFX7-NEXT: v_mov_b32_e32 v4, v2
|
|
; GFX7-NEXT: s_mov_b32 s1, 4
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: s_mov_b32 s2, s0
|
|
; GFX7-NEXT: buffer_atomic_cmpswap v[3:4], v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: buffer_wbinvl1
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, v3
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_cmpxchg_vgpr_ptr_offset4294967296:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_mov_b32 s0, 0
|
|
; GFX12-NEXT: s_mov_b32 s1, 4
|
|
; GFX12-NEXT: v_mov_b32_e32 v4, v2
|
|
; GFX12-NEXT: v_dual_mov_b32 v6, s1 :: v_dual_mov_b32 v5, s0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v5
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v6, vcc_lo
|
|
; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[0:1], v[3:4], off th:TH_ATOMIC_RETURN
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: global_inv scope:SCOPE_DEV
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4294967296
|
|
%result.struct = cmpxchg ptr addrspace(1) %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst
|
|
%result = extractvalue { i32, i1 } %result.struct, 0
|
|
%cast = bitcast i32 %result to float
|
|
ret float %cast
|
|
}
|
|
|
|
define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_vgpr_offset(ptr addrspace(1) inreg %ptr, i32 %voffset, i32 %old, i32 %in) {
|
|
; GFX6-LABEL: mubuf_cmpxchg_sgpr_ptr_vgpr_offset:
|
|
; GFX6: ; %bb.0:
|
|
; GFX6-NEXT: v_mov_b32_e32 v3, v1
|
|
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX6-NEXT: s_mov_b32 s0, s2
|
|
; GFX6-NEXT: s_mov_b32 s1, s3
|
|
; GFX6-NEXT: s_mov_b32 s2, 0
|
|
; GFX6-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX6-NEXT: buffer_atomic_cmpswap v[2:3], v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX6-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX6-NEXT: buffer_wbinvl1
|
|
; GFX6-NEXT: v_mov_b32_e32 v0, v2
|
|
; GFX6-NEXT: s_waitcnt expcnt(0)
|
|
; GFX6-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX7-LABEL: mubuf_cmpxchg_sgpr_ptr_vgpr_offset:
|
|
; GFX7: ; %bb.0:
|
|
; GFX7-NEXT: v_mov_b32_e32 v3, v1
|
|
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
|
|
; GFX7-NEXT: s_mov_b32 s0, s2
|
|
; GFX7-NEXT: s_mov_b32 s1, s3
|
|
; GFX7-NEXT: s_mov_b32 s2, 0
|
|
; GFX7-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX7-NEXT: buffer_atomic_cmpswap v[2:3], v[0:1], s[0:3], 0 addr64 glc
|
|
; GFX7-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX7-NEXT: buffer_wbinvl1
|
|
; GFX7-NEXT: v_mov_b32_e32 v0, v2
|
|
; GFX7-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: mubuf_cmpxchg_sgpr_ptr_vgpr_offset:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_mov_b32_e32 v3, v1
|
|
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX12-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
|
|
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v5, v1, vcc_lo
|
|
; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[0:1], v[2:3], off th:TH_ATOMIC_RETURN
|
|
; GFX12-NEXT: s_wait_loadcnt 0x0
|
|
; GFX12-NEXT: global_inv scope:SCOPE_DEV
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
%gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %voffset
|
|
%result.struct = cmpxchg ptr addrspace(1) %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst
|
|
%result = extractvalue { i32, i1 } %result.struct, 0
|
|
%cast = bitcast i32 %result to float
|
|
ret float %cast
|
|
}
|