110 lines
4 KiB
LLVM
110 lines
4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s -check-prefix=GFX9
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck %s -check-prefix=GFX12
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; We have an indirect call with a known set of callees, which are
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; known to not need any special inputs. The ABI still needs to use the
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; register
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; FIXME: Passing real values for workitem ID, and 0s that can be undef
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define amdgpu_kernel void @indirect_call_known_no_special_inputs() {
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; GFX9-LABEL: indirect_call_known_no_special_inputs:
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; GFX9: ; %bb.0: ; %bb
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; GFX9-NEXT: s_add_u32 flat_scratch_lo, s4, s7
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; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
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; GFX9-NEXT: s_add_u32 s0, s0, s7
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; GFX9-NEXT: s_addc_u32 s1, s1, 0
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; GFX9-NEXT: s_mov_b64 s[4:5], 0
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; GFX9-NEXT: s_load_dword s7, s[4:5], 0x0
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; GFX9-NEXT: s_getpc_b64 s[4:5]
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; GFX9-NEXT: s_add_u32 s4, s4, wobble@gotpcrel32@lo+4
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; GFX9-NEXT: s_addc_u32 s5, s5, wobble@gotpcrel32@hi+12
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; GFX9-NEXT: s_getpc_b64 s[8:9]
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; GFX9-NEXT: s_add_u32 s8, s8, snork@gotpcrel32@lo+4
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; GFX9-NEXT: s_addc_u32 s9, s9, snork@gotpcrel32@hi+12
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; GFX9-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x0
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; GFX9-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x0
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; GFX9-NEXT: s_mov_b64 s[8:9], 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_and_b32 s4, 1, s7
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; GFX9-NEXT: s_cmp_eq_u32 s4, 1
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; GFX9-NEXT: v_mov_b32_e32 v31, v0
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; GFX9-NEXT: s_cselect_b32 s5, s13, s11
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; GFX9-NEXT: s_cselect_b32 s4, s12, s10
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; GFX9-NEXT: s_mov_b32 s12, s6
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: v_mov_b32_e32 v4, 0
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; GFX9-NEXT: s_mov_b32 s32, 0
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; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GFX9-NEXT: s_endpgm
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;
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; GFX12-LABEL: indirect_call_known_no_special_inputs:
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; GFX12: ; %bb.0: ; %bb
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; GFX12-NEXT: s_getpc_b64 s[2:3]
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; GFX12-NEXT: s_sext_i32_i16 s3, s3
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; GFX12-NEXT: s_add_co_u32 s2, s2, snork@gotpcrel32@lo+8
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; GFX12-NEXT: s_add_co_ci_u32 s3, s3, snork@gotpcrel32@hi+16
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; GFX12-NEXT: s_mov_b64 s[0:1], 0
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; GFX12-NEXT: s_getpc_b64 s[4:5]
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; GFX12-NEXT: s_sext_i32_i16 s5, s5
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; GFX12-NEXT: s_add_co_u32 s4, s4, wobble@gotpcrel32@lo+8
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; GFX12-NEXT: s_add_co_ci_u32 s5, s5, wobble@gotpcrel32@hi+16
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; GFX12-NEXT: s_load_u8 s6, s[0:1], 0x0
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; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
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; GFX12-NEXT: s_load_b64 s[2:3], s[4:5], 0x0
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; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
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; GFX12-NEXT: v_mov_b32_e32 v31, v0
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; GFX12-NEXT: s_mov_b64 s[8:9], 0
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; GFX12-NEXT: s_mov_b32 s32, 0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_and_b32 s4, 1, s6
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
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; GFX12-NEXT: s_cmp_eq_u32 s4, 1
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; GFX12-NEXT: s_cselect_b32 s1, s3, s1
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; GFX12-NEXT: s_cselect_b32 s0, s2, s0
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; GFX12-NEXT: s_swappc_b64 s[30:31], s[0:1]
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; GFX12-NEXT: s_endpgm
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bb:
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%cond = load i1, ptr addrspace(4) null
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%tmp = select i1 %cond, ptr @wobble, ptr @snork
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call void %tmp(ptr undef, i32 undef, ptr undef)
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ret void
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}
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define void @wobble() {
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; GFX9-LABEL: wobble:
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; GFX9: ; %bb.0: ; %bb
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: wobble:
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; GFX12: ; %bb.0: ; %bb
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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bb:
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ret void
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}
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define void @snork() {
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; GFX9-LABEL: snork:
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; GFX9: ; %bb.0: ; %bb
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-LABEL: snork:
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; GFX12: ; %bb.0: ; %bb
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; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-NEXT: s_wait_expcnt 0x0
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; GFX12-NEXT: s_wait_samplecnt 0x0
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; GFX12-NEXT: s_wait_bvhcnt 0x0
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; GFX12-NEXT: s_wait_kmcnt 0x0
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; GFX12-NEXT: s_setpc_b64 s[30:31]
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bb:
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ret void
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}
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