256 lines
11 KiB
LLVM
256 lines
11 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,ALIGNED,SPLIT %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,ALIGNED,SPLIT %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,ALIGNED,SPLIT %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,ALIGNED,VECT %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -mattr=+cumode,+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,UNALIGNED,VECT %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,ALIGNED,VECT %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -mattr=+cumode < %s | FileCheck -check-prefixes=GCN,ALIGNED,VECT %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -mattr=+cumode,+unaligned-access-mode < %s | FileCheck -check-prefixes=GCN,UNALIGNED,VECT %s
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; GCN-LABEL: test_local_misaligned_v2:
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; GCN-DAG: ds_{{read2|load_2addr}}_b32
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; GCN-DAG: ds_{{write2|store_2addr}}_b32
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define amdgpu_kernel void @test_local_misaligned_v2(ptr addrspace(3) %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid
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%load = load <2 x i32>, ptr addrspace(3) %gep, align 4
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%v1 = extractelement <2 x i32> %load, i32 0
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%v2 = extractelement <2 x i32> %load, i32 1
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%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
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%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
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store <2 x i32> %v4, ptr addrspace(3) %gep, align 4
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ret void
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}
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; GCN-LABEL: test_local_misaligned_v4:
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; GCN-DAG: ds_{{read2|load_2addr}}_b32
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; GCN-DAG: ds_{{read2|load_2addr}}_b32
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; GCN-DAG: ds_{{write2|store_2addr}}_b32
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; GCN-DAG: ds_{{write2|store_2addr}}_b32
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define amdgpu_kernel void @test_local_misaligned_v4(ptr addrspace(3) %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid
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%load = load <4 x i32>, ptr addrspace(3) %gep, align 4
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%v1 = extractelement <4 x i32> %load, i32 0
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%v2 = extractelement <4 x i32> %load, i32 1
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%v3 = extractelement <4 x i32> %load, i32 2
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%v4 = extractelement <4 x i32> %load, i32 3
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%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
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%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
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%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
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%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
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store <4 x i32> %v8, ptr addrspace(3) %gep, align 4
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ret void
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}
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; GCN-LABEL: test_local_misaligned_v3:
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; GCN-DAG: ds_{{read2|load_2addr}}_b32
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; GCN-DAG: ds_{{read|load}}_b32
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; GCN-DAG: ds_{{write2|store_2addr}}_b32
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; GCN-DAG: ds_{{write|store}}_b32
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define amdgpu_kernel void @test_local_misaligned_v3(ptr addrspace(3) %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid
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%load = load <3 x i32>, ptr addrspace(3) %gep, align 4
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%v1 = extractelement <3 x i32> %load, i32 0
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%v2 = extractelement <3 x i32> %load, i32 1
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%v3 = extractelement <3 x i32> %load, i32 2
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%v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
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%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
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%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
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store <3 x i32> %v7, ptr addrspace(3) %gep, align 4
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ret void
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}
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; GCN-LABEL: test_flat_misaligned_v2:
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; VECT-DAG: flat_load_{{dwordx2|b64}} v
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; VECT-DAG: flat_store_{{dwordx2|b64}} v
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; SPLIT-DAG: flat_load_{{dword|b32}} v
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; SPLIT-DAG: flat_load_{{dword|b32}} v
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; SPLIT-DAG: flat_store_{{dword|b32}} v
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; SPLIT-DAG: flat_store_{{dword|b32}} v
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define amdgpu_kernel void @test_flat_misaligned_v2(ptr %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr %arg, i32 %lid
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%load = load <2 x i32>, ptr %gep, align 4
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%v1 = extractelement <2 x i32> %load, i32 0
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%v2 = extractelement <2 x i32> %load, i32 1
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%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
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%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
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store <2 x i32> %v4, ptr %gep, align 4
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ret void
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}
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; GCN-LABEL: test_flat_misaligned_v4:
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; VECT-DAG: flat_load_{{dwordx4|b128}} v
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; VECT-DAG: flat_store_{{dwordx4|b128}} v
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; SPLIT-DAG: flat_load_{{dword|b32}} v
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; SPLIT-DAG: flat_load_{{dword|b32}} v
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; SPLIT-DAG: flat_load_{{dword|b32}} v
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; SPLIT-DAG: flat_load_{{dword|b32}} v
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; SPLIT-DAG: flat_store_{{dword|b32}} v
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; SPLIT-DAG: flat_store_{{dword|b32}} v
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; SPLIT-DAG: flat_store_{{dword|b32}} v
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; SPLIT-DAG: flat_store_{{dword|b32}} v
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define amdgpu_kernel void @test_flat_misaligned_v4(ptr %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr %arg, i32 %lid
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%load = load <4 x i32>, ptr %gep, align 4
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%v1 = extractelement <4 x i32> %load, i32 0
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%v2 = extractelement <4 x i32> %load, i32 1
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%v3 = extractelement <4 x i32> %load, i32 2
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%v4 = extractelement <4 x i32> %load, i32 3
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%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
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%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
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%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
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%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
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store <4 x i32> %v8, ptr %gep, align 4
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ret void
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}
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; GCN-LABEL: test_flat_misaligned_v3:
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; VECT-DAG: flat_load_{{dwordx3|b96}} v
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; VECT-DAG: flat_store_{{dwordx3|b96}} v
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; SPLIT-DAG: flat_load_{{dword|b32}} v
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; SPLIT-DAG: flat_load_{{dword|b32}} v
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; SPLIT-DAG: flat_load_{{dword|b32}} v
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; SPLIT-DAG: flat_store_{{dword|b32}} v
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; SPLIT-DAG: flat_store_{{dword|b32}} v
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; SPLIT-DAG: flat_store_{{dword|b32}} v
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define amdgpu_kernel void @test_flat_misaligned_v3(ptr %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr %arg, i32 %lid
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%load = load <3 x i32>, ptr %gep, align 4
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%v1 = extractelement <3 x i32> %load, i32 0
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%v2 = extractelement <3 x i32> %load, i32 1
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%v3 = extractelement <3 x i32> %load, i32 2
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%v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
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%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
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%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
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store <3 x i32> %v7, ptr %gep, align 4
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ret void
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}
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; GCN-LABEL: test_local_aligned_v2:
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; GCN-DAG: ds_{{read|load}}_b64
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; GCN-DAG: ds_{{write|store}}_b64
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define amdgpu_kernel void @test_local_aligned_v2(ptr addrspace(3) %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid
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%load = load <2 x i32>, ptr addrspace(3) %gep, align 8
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%v1 = extractelement <2 x i32> %load, i32 0
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%v2 = extractelement <2 x i32> %load, i32 1
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%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
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%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
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store <2 x i32> %v4, ptr addrspace(3) %gep, align 8
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ret void
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}
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; GCN-LABEL: test_local_aligned_v3:
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; GCN-DAG: ds_{{read|load}}_b96
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; GCN-DAG: ds_{{write|store}}_b96
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define amdgpu_kernel void @test_local_aligned_v3(ptr addrspace(3) %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid
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%load = load <3 x i32>, ptr addrspace(3) %gep, align 16
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%v1 = extractelement <3 x i32> %load, i32 0
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%v2 = extractelement <3 x i32> %load, i32 1
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%v3 = extractelement <3 x i32> %load, i32 2
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%v5 = insertelement <3 x i32> undef, i32 %v3, i32 0
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%v6 = insertelement <3 x i32> %v5, i32 %v1, i32 1
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%v7 = insertelement <3 x i32> %v6, i32 %v2, i32 2
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store <3 x i32> %v7, ptr addrspace(3) %gep, align 16
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ret void
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}
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; GCN-LABEL: test_flat_aligned_v2:
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; GCN-DAG: flat_load_{{dwordx2|b64}} v
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; GCN-DAG: flat_store_{{dwordx2|b64}} v
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define amdgpu_kernel void @test_flat_aligned_v2(ptr %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr %arg, i32 %lid
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%load = load <2 x i32>, ptr %gep, align 8
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%v1 = extractelement <2 x i32> %load, i32 0
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%v2 = extractelement <2 x i32> %load, i32 1
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%v3 = insertelement <2 x i32> undef, i32 %v2, i32 0
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%v4 = insertelement <2 x i32> %v3, i32 %v1, i32 1
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store <2 x i32> %v4, ptr %gep, align 8
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ret void
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}
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; GCN-LABEL: test_flat_aligned_v4:
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; GCN-DAG: flat_load_{{dwordx4|b128}} v
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; GCN-DAG: flat_store_{{dwordx4|b128}} v
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define amdgpu_kernel void @test_flat_aligned_v4(ptr %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr %arg, i32 %lid
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%load = load <4 x i32>, ptr %gep, align 16
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%v1 = extractelement <4 x i32> %load, i32 0
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%v2 = extractelement <4 x i32> %load, i32 1
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%v3 = extractelement <4 x i32> %load, i32 2
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%v4 = extractelement <4 x i32> %load, i32 3
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%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
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%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
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%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
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%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
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store <4 x i32> %v8, ptr %gep, align 16
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ret void
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}
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; GCN-LABEL: test_local_v4_aligned8:
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; ALIGNED-DAG: ds_{{read2|load_2addr}}_b64
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; ALIGNED-DAG: ds_{{write2|store_2addr}}_b64
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; UNALIGNED-DAG: ds_{{read2|load_2addr}}_b64
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; UNALIGNED-DAG: ds_{{write2|store_2addr}}_b64
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define amdgpu_kernel void @test_local_v4_aligned8(ptr addrspace(3) %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr addrspace(3) %arg, i32 %lid
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%load = load <4 x i32>, ptr addrspace(3) %gep, align 8
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%v1 = extractelement <4 x i32> %load, i32 0
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%v2 = extractelement <4 x i32> %load, i32 1
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%v3 = extractelement <4 x i32> %load, i32 2
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%v4 = extractelement <4 x i32> %load, i32 3
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%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
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%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
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%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
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%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
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store <4 x i32> %v8, ptr addrspace(3) %gep, align 8
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ret void
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}
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; GCN-LABEL: test_flat_v4_aligned8:
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; VECT-DAG: flat_load_{{dwordx4|b128}} v
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; VECT-DAG: flat_store_{{dwordx4|b128}} v
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; SPLIT-DAG: flat_load_{{dwordx2|b64}} v
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; SPLIT-DAG: flat_load_{{dwordx2|b64}} v
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; SPLIT-DAG: flat_store_{{dwordx2|b64}} v
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; SPLIT-DAG: flat_store_{{dwordx2|b64}} v
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define amdgpu_kernel void @test_flat_v4_aligned8(ptr %arg) {
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bb:
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%lid = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, ptr %arg, i32 %lid
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%load = load <4 x i32>, ptr %gep, align 8
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%v1 = extractelement <4 x i32> %load, i32 0
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%v2 = extractelement <4 x i32> %load, i32 1
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%v3 = extractelement <4 x i32> %load, i32 2
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%v4 = extractelement <4 x i32> %load, i32 3
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%v5 = insertelement <4 x i32> undef, i32 %v4, i32 0
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%v6 = insertelement <4 x i32> %v5, i32 %v3, i32 1
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%v7 = insertelement <4 x i32> %v6, i32 %v2, i32 2
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%v8 = insertelement <4 x i32> %v7, i32 %v1, i32 3
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store <4 x i32> %v8, ptr %gep, align 8
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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