samvv/bolt
1
0
Fork 0
Code Issues 24 Pull requests Projects Releases Packages Wiki Activity Actions
bolt/deps/llvm-18.1.8/llvm/test/CodeGen/AMDGPU/load-local-i32.ll
Sam Vervaeck 174b6f4d4e
Embed LLVM 18.1.8
2025-02-14 19:21:04 +01:00

281 lines
9.2 KiB
LLVM
Raw Blame History

; RUN: llc -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global,-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SICIVI,FUNC %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global,-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx908 -mattr=-flat-for-global,-enable-ds128 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,FUNC %s
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s
; Testing for ds_read/write_128
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=SI,FUNC %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=+enable-ds128 < %s | FileCheck -check-prefixes=CIVI,FUNC %s
; FUNC-LABEL: {{^}}local_load_i32:
; GCN-NOT: s_wqm_b64
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
; GCN: ds_read_b32
; EG: LDS_READ_RET
define amdgpu_kernel void @local_load_i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
entry:
%ld = load i32, ptr addrspace(3) %in
store i32 %ld, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_load_v2i32:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
; GCN: ds_read_b64
define amdgpu_kernel void @local_load_v2i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
entry:
%ld = load <2 x i32>, ptr addrspace(3) %in
store <2 x i32> %ld, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_load_v3i32:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
; SI-DAG: ds_read_b64
; SI-DAG: ds_read_b32
; CIVI-DAG: ds_read_b96
define amdgpu_kernel void @local_load_v3i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
entry:
%ld = load <3 x i32>, ptr addrspace(3) %in
store <3 x i32> %ld, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_load_v4i32:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
define amdgpu_kernel void @local_load_v4i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
entry:
%ld = load <4 x i32>, ptr addrspace(3) %in
store <4 x i32> %ld, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_load_v8i32:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
define amdgpu_kernel void @local_load_v8i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
entry:
%ld = load <8 x i32>, ptr addrspace(3) %in
store <8 x i32> %ld, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_load_v16i32:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7{{$}}
; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5{{$}}
; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:6 offset1:7
; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:4 offset1:5
; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:2 offset1:3
; GCN-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset1:1
define amdgpu_kernel void @local_load_v16i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
entry:
%ld = load <16 x i32>, ptr addrspace(3) %in
store <16 x i32> %ld, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_zextload_i32_to_i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_zextload_i32_to_i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load i32, ptr addrspace(3) %in
%ext = zext i32 %ld to i64
store i64 %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_sextload_i32_to_i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_sextload_i32_to_i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load i32, ptr addrspace(3) %in
%ext = sext i32 %ld to i64
store i64 %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_zextload_v1i32_to_v1i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_zextload_v1i32_to_v1i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <1 x i32>, ptr addrspace(3) %in
%ext = zext <1 x i32> %ld to <1 x i64>
store <1 x i64> %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_sextload_v1i32_to_v1i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_sextload_v1i32_to_v1i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <1 x i32>, ptr addrspace(3) %in
%ext = sext <1 x i32> %ld to <1 x i64>
store <1 x i64> %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_zextload_v2i32_to_v2i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_zextload_v2i32_to_v2i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <2 x i32>, ptr addrspace(3) %in
%ext = zext <2 x i32> %ld to <2 x i64>
store <2 x i64> %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_sextload_v2i32_to_v2i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_sextload_v2i32_to_v2i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <2 x i32>, ptr addrspace(3) %in
%ext = sext <2 x i32> %ld to <2 x i64>
store <2 x i64> %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_zextload_v4i32_to_v4i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_zextload_v4i32_to_v4i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <4 x i32>, ptr addrspace(3) %in
%ext = zext <4 x i32> %ld to <4 x i64>
store <4 x i64> %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_sextload_v4i32_to_v4i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_sextload_v4i32_to_v4i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <4 x i32>, ptr addrspace(3) %in
%ext = sext <4 x i32> %ld to <4 x i64>
store <4 x i64> %ext, ptr addrspace(3) %out
ret void
}
; Tests if ds_read/write_b128 gets generated for the 16 byte aligned load.
; FUNC-LABEL: {{^}}local_v4i32_to_128:
; SI-NOT: ds_read_b128
; SI-NOT: ds_write_b128
; CIVI: ds_read_b128
; CIVI: ds_write_b128
; EG: LDS_READ_RET
; EG: LDS_READ_RET
; EG: LDS_READ_RET
; EG: LDS_READ_RET
define amdgpu_kernel void @local_v4i32_to_128(ptr addrspace(3) %out, ptr addrspace(3) %in) {
%ld = load <4 x i32>, ptr addrspace(3) %in, align 16
store <4 x i32> %ld, ptr addrspace(3) %out, align 16
ret void
}
; FUNC-LABEL: {{^}}local_zextload_v8i32_to_v8i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_zextload_v8i32_to_v8i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <8 x i32>, ptr addrspace(3) %in
%ext = zext <8 x i32> %ld to <8 x i64>
store <8 x i64> %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_sextload_v8i32_to_v8i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_sextload_v8i32_to_v8i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <8 x i32>, ptr addrspace(3) %in
%ext = sext <8 x i32> %ld to <8 x i64>
store <8 x i64> %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_sextload_v16i32_to_v16i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_sextload_v16i32_to_v16i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <16 x i32>, ptr addrspace(3) %in
%ext = sext <16 x i32> %ld to <16 x i64>
store <16 x i64> %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_zextload_v16i32_to_v16i64
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_zextload_v16i32_to_v16i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <16 x i32>, ptr addrspace(3) %in
%ext = zext <16 x i32> %ld to <16 x i64>
store <16 x i64> %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_sextload_v32i32_to_v32i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_sextload_v32i32_to_v32i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <32 x i32>, ptr addrspace(3) %in
%ext = sext <32 x i32> %ld to <32 x i64>
store <32 x i64> %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_zextload_v32i32_to_v32i64:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
define amdgpu_kernel void @local_zextload_v32i32_to_v32i64(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <32 x i32>, ptr addrspace(3) %in
%ext = zext <32 x i32> %ld to <32 x i64>
store <32 x i64> %ext, ptr addrspace(3) %out
ret void
}
; FUNC-LABEL: {{^}}local_load_v32i32:
; SICIVI: s_mov_b32 m0, -1
; GFX9-NOT: m0
; GFX9-NOT: accvgpr
define amdgpu_kernel void @local_load_v32i32(ptr addrspace(3) %out, ptr addrspace(3) %in) #0 {
%ld = load <32 x i32>, ptr addrspace(3) %in
store <32 x i32> %ld, ptr addrspace(3) %out
ret void
}
attributes #0 = { nounwind }
Reference in a new issue View git blame Copy permalink