232 lines
6.5 KiB
YAML
232 lines
6.5 KiB
YAML
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-optimize-exec-masking-pre-ra,greedy -verify-machineinstrs -o - %s
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# This sample can trigger a "Non-empty but used interval" assert in regalloc if
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# SIOptimizeExecMaskingPreRA does not update live intervals correctly.
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---
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name: foo
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tracksRegLiveness: true
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body: |
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bb.0:
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%0:sreg_32 = IMPLICIT_DEF
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%1:sreg_32_xm0_xexec = IMPLICIT_DEF
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%2:sreg_64_xexec = IMPLICIT_DEF
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%3:sgpr_32 = IMPLICIT_DEF
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%4:sreg_32_xexec_hi = IMPLICIT_DEF
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%5:sreg_32 = IMPLICIT_DEF
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%6:sreg_32 = IMPLICIT_DEF
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%7:sreg_32 = IMPLICIT_DEF
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%8:sreg_32 = IMPLICIT_DEF
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%9:sreg_32 = IMPLICIT_DEF
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%10:sreg_32 = IMPLICIT_DEF
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%11:sreg_32 = IMPLICIT_DEF
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%12:sreg_64_xexec = IMPLICIT_DEF
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%13:sreg_64_xexec = IMPLICIT_DEF
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%14:sreg_32 = IMPLICIT_DEF
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%15:sreg_32 = IMPLICIT_DEF
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%16:sreg_32 = IMPLICIT_DEF
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%17:sreg_32 = IMPLICIT_DEF
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%18:sgpr_32 = IMPLICIT_DEF
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$exec_lo = S_MOV_B32_term undef %9
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S_BRANCH %bb.2
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bb.1:
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$exec_lo = S_XOR_B32_term $exec_lo, undef %10, implicit-def $scc
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S_CBRANCH_EXECZ %bb.39, implicit $exec
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S_BRANCH %bb.32
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bb.2:
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S_CMP_EQ_U32 %15, undef %15, implicit-def $scc
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%19:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed undef $scc
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%20:sreg_32 = IMPLICIT_DEF
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dead $vcc_lo = COPY undef %20
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S_CBRANCH_VCCNZ %bb.3, implicit $vcc
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S_BRANCH %bb.3
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bb.3:
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dead $vcc_lo = S_AND_B32 $exec_lo, undef %19, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.6, implicit $vcc
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S_BRANCH %bb.4
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bb.4:
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%21:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %19, implicit $exec
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%22:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, undef %21, implicit $exec
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dead $vcc_lo = S_AND_B32 $exec_lo, undef %22, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.7, implicit $vcc
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S_BRANCH %bb.5
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bb.5:
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S_BRANCH %bb.7
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bb.6:
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$vcc_lo = COPY %20
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%18:sgpr_32 = COPY %18
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S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
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S_BRANCH %bb.2
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bb.7:
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%23:sreg_32 = S_AND_B32 undef %20, %9, implicit-def dead $scc
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$exec_lo = S_MOV_B32_term undef %23
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S_CBRANCH_EXECZ %bb.10, implicit $exec
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S_BRANCH %bb.9
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bb.8:
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%24:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %13, undef %21, 0, 0, implicit $exec
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S_BRANCH %bb.28
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bb.9:
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S_BRANCH %bb.11
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bb.10:
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$exec_lo = S_XOR_B32_term $exec_lo, %23, implicit-def $scc
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S_CBRANCH_EXECZ %bb.31, implicit $exec
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S_BRANCH %bb.8
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bb.11:
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%25:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %2, undef %21, 0, 0, implicit $exec
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$exec_lo = S_MOV_B32_term undef %23
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S_CBRANCH_EXECZ %bb.12, implicit $exec
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S_BRANCH %bb.14
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bb.12:
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$exec_lo = S_XOR_B32_term $exec_lo, undef %23, implicit-def $scc
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S_CBRANCH_EXECZ %bb.15, implicit $exec
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S_BRANCH %bb.13
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bb.13:
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$exec_lo = S_MOV_B32_term undef %23
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S_CBRANCH_EXECZ %bb.15, implicit $exec
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S_BRANCH %bb.15
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bb.14:
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%26:vgpr_32 = V_BFI_B32_e64 2147483647, %3, undef %25, implicit $exec
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%27:vgpr_32 = V_CNDMASK_B32_e64 0, undef %26, 0, 2143289344, %1, implicit $exec
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dead %28:vgpr_32, %29:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %12.sub0, undef %27, 0, implicit $exec
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%30:vgpr_32, dead %31:sreg_32_xm0_xexec = V_ADDC_U32_e64 %12.sub1, undef %27, undef %22, 0, implicit $exec
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SCRATCH_STORE_DWORD_SADDR undef %27, %4, 0, 0, implicit $exec, implicit $flat_scr
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S_BRANCH %bb.12
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bb.15:
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%32:sreg_32 = IMPLICIT_DEF
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$exec_lo = S_MOV_B32_term undef %32
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S_CBRANCH_EXECZ %bb.17, implicit $exec
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S_BRANCH %bb.16
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bb.16:
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%33:sreg_32 = S_AND_B32 undef %32, %16, implicit-def dead $scc
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$exec_lo = S_MOV_B32_term undef %33
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S_CBRANCH_EXECZ %bb.17, implicit $exec
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S_BRANCH %bb.17
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bb.17:
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$exec_lo = S_XOR_B32_term $exec_lo, undef %32, implicit-def $scc
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S_CBRANCH_EXECZ %bb.30, implicit $exec
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S_BRANCH %bb.18
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bb.18:
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%34:sreg_32 = IMPLICIT_DEF
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%35:sreg_32 = S_AND_B32 undef %34, %17, implicit-def dead $scc
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$exec_lo = S_MOV_B32_term undef %35
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S_CBRANCH_EXECZ %bb.20, implicit $exec
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S_BRANCH %bb.19
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bb.19:
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dead %36:vgpr_32, $sgpr_null = V_ADD_CO_U32_e64 %14, undef %25, 0, implicit $exec
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%37:sreg_32 = IMPLICIT_DEF
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S_BRANCH %bb.21
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bb.20:
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$exec_lo = S_OR_B32 $exec_lo, %34, implicit-def $scc
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S_BRANCH %bb.30
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bb.21:
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%38:sreg_32 = IMPLICIT_DEF
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$exec_lo = S_MOV_B32_term undef %38
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S_CBRANCH_EXECZ %bb.23, implicit $exec
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S_BRANCH %bb.22
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bb.22:
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S_BRANCH %bb.24
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bb.23:
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S_BRANCH %bb.26
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bb.24:
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%39:sreg_32 = S_AND_B32 undef %38, %11, implicit-def dead $scc
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$exec_lo = S_MOV_B32_term undef %39
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S_CBRANCH_EXECZ %bb.38, implicit $exec
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S_BRANCH %bb.25
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bb.25:
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%40:sreg_32 = S_AND_B32 %5, $exec_lo, implicit-def dead $scc
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S_BRANCH %bb.38
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bb.26:
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%37:sreg_32 = S_OR_B32 %38, %37, implicit-def $scc
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$exec_lo = S_ANDN2_B32_term $exec_lo, undef %37, implicit-def $scc
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S_CBRANCH_EXECNZ %bb.21, implicit $exec
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S_BRANCH %bb.27
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bb.27:
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%41:sreg_32 = S_OR_B32 undef %37, %35, implicit-def $scc
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$exec_lo = S_ANDN2_B32_term $exec_lo, undef %35, implicit-def $scc
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S_CBRANCH_EXECNZ %bb.21, implicit $exec
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S_BRANCH %bb.20
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bb.28:
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dead $vcc_lo = S_AND_B32 $exec_lo, %22, implicit-def dead $scc
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S_CBRANCH_VCCNZ %bb.29, implicit $vcc
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S_BRANCH %bb.29
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bb.29:
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$exec_lo = S_ANDN2_B32_term $exec_lo, undef %23, implicit-def $scc
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S_CBRANCH_EXECNZ %bb.28, implicit $exec
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S_BRANCH %bb.31
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bb.30:
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$exec_lo = S_OR_B32 $exec_lo, %32, implicit-def $scc
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S_BRANCH %bb.10
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bb.31:
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%42:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 undef %23, %21, implicit $exec
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$vcc_lo = S_AND_B32 $exec_lo, undef %42, implicit-def dead $scc
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S_CBRANCH_VCCZ %bb.6, implicit killed $vcc
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bb.32:
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%43:sreg_32 = S_AND_B32 %10, %8, implicit-def dead $scc
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$exec_lo = S_MOV_B32_term undef %43
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S_CBRANCH_EXECZ %bb.37, implicit $exec
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S_BRANCH %bb.33
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bb.33:
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%44:sreg_32 = S_AND_B32 undef %43, %0, implicit-def dead $scc
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$exec_lo = S_MOV_B32_term undef %44
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S_CBRANCH_EXECZ %bb.37, implicit $exec
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S_BRANCH %bb.34
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bb.34:
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%45:sreg_32 = S_AND_B32 undef %44, %6, implicit-def dead $scc
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$exec_lo = S_MOV_B32_term undef %45
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S_CBRANCH_EXECZ %bb.37, implicit $exec
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S_BRANCH %bb.35
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bb.35:
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%46:sreg_32 = S_AND_B32 undef %45, %7, implicit-def dead $scc
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$exec_lo = S_MOV_B32_term undef %46
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S_CBRANCH_EXECZ %bb.36, implicit $exec
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S_BRANCH %bb.37
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bb.36:
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S_BRANCH %bb.37
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bb.37:
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dead $vcc_lo = COPY undef %47:sreg_32
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S_BRANCH %bb.39
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bb.38:
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S_BRANCH %bb.26
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bb.39:
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SI_RETURN
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...
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