121 lines
4.1 KiB
LLVM
121 lines
4.1 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -O3 -mtriple=armv6-apple-darwin -relocation-model=pic -mcpu=arm1136jf-s -arm-atomic-cfg-tidy=0 | FileCheck %s
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; rdar://8959122 illegal register operands for UMULL instruction
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; in cfrac nightly test.
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; Armv6 generates a umull that must write to two distinct destination regs.
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; ModuleID = 'bugpoint-reduced-simplified.bc'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32"
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target triple = "armv6-apple-darwin10"
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define void @ptoa(i1 %tst, ptr %p8, i8 %val8) nounwind {
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entry:
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br i1 false, label %bb3, label %bb
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bb: ; preds = %entry
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br label %bb3
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bb3: ; preds = %bb, %entry
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%0 = call noalias ptr @malloc() nounwind
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br i1 %tst, label %bb46, label %bb8
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bb8: ; preds = %bb3
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store volatile i8 0, ptr %0, align 1
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%1 = call i32 @ptou() nounwind
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%2 = udiv i32 %1, 10
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%3 = urem i32 %2, 10
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%4 = icmp ult i32 %3, 10
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%5 = trunc i32 %3 to i8
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%6 = or i8 %5, 48
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%7 = add i8 %5, 87
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%iftmp.5.0.1 = select i1 %4, i8 %6, i8 %7
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store volatile i8 %iftmp.5.0.1, ptr %p8, align 1
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%8 = udiv i32 %1, 100
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%9 = urem i32 %8, 10
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%10 = icmp ult i32 %9, 10
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%11 = trunc i32 %9 to i8
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%12 = or i8 %11, 48
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%13 = add i8 %11, 87
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%iftmp.5.0.2 = select i1 %10, i8 %12, i8 %13
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store volatile i8 %iftmp.5.0.2, ptr %p8, align 1
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%14 = udiv i32 %1, 10000
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%15 = urem i32 %14, 10
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%16 = icmp ult i32 %15, 10
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%17 = trunc i32 %15 to i8
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%18 = or i8 %17, 48
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%19 = add i8 %17, 87
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%iftmp.5.0.4 = select i1 %16, i8 %18, i8 %19
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store volatile i8 %iftmp.5.0.4, ptr null, align 1
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%20 = udiv i32 %1, 100000
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%21 = urem i32 %20, 10
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%22 = icmp ult i32 %21, 10
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%iftmp.5.0.5 = select i1 %22, i8 0, i8 %val8
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store volatile i8 %iftmp.5.0.5, ptr %p8, align 1
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%23 = udiv i32 %1, 1000000
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%24 = urem i32 %23, 10
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%25 = icmp ult i32 %24, 10
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%26 = trunc i32 %24 to i8
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%27 = or i8 %26, 48
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%28 = add i8 %26, 87
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%iftmp.5.0.6 = select i1 %25, i8 %27, i8 %28
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store volatile i8 %iftmp.5.0.6, ptr %p8, align 1
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%29 = udiv i32 %1, 10000000
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%30 = urem i32 %29, 10
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%31 = icmp ult i32 %30, 10
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%32 = trunc i32 %30 to i8
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%33 = or i8 %32, 48
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%34 = add i8 %32, 87
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%iftmp.5.0.7 = select i1 %31, i8 %33, i8 %34
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store volatile i8 %iftmp.5.0.7, ptr %p8, align 1
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%35 = udiv i32 %1, 100000000
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%36 = urem i32 %35, 10
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%37 = icmp ult i32 %36, 10
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%38 = trunc i32 %36 to i8
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%39 = or i8 %38, 48
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%40 = add i8 %38, 87
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%iftmp.5.0.8 = select i1 %37, i8 %39, i8 %40
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store volatile i8 %iftmp.5.0.8, ptr null, align 1
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br label %bb46
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bb46: ; preds = %bb3
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ret void
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}
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declare noalias ptr @malloc() nounwind
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declare i32 @ptou()
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