139 lines
7 KiB
LLVM
139 lines
7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -mtriple=thumbv7-unknown-linux-android -arm-parallel-dsp -S %s -o - | FileCheck %s
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define void @undef_no_return(ptr %a) {
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; CHECK-LABEL: @undef_no_return(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, ptr [[A:%.*]], i32 3
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; CHECK-NEXT: [[INCDEC_PTR29:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 4
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[INCDEC_PTR21]], align 2
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[INCDEC_PTR21]], align 2
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; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16
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; CHECK-NEXT: [[TMP4:%.*]] = sext i16 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = lshr i32 [[TMP2]], 16
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16
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; CHECK-NEXT: [[TMP7:%.*]] = sext i16 [[TMP6]] to i32
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; CHECK-NEXT: [[CONV25:%.*]] = sext i16 [[TMP0]] to i32
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; CHECK-NEXT: [[UGLYGEP15:%.*]] = getelementptr i8, ptr undef, i32 undef
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; CHECK-NEXT: [[SCEVGEP17:%.*]] = getelementptr i16, ptr [[UGLYGEP15]], i32 7
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; CHECK-NEXT: [[TMP8:%.*]] = load i16, ptr [[SCEVGEP17]], align 2
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; CHECK-NEXT: [[UGLYGEP12:%.*]] = getelementptr i8, ptr undef, i32 undef
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; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i16, ptr [[UGLYGEP12]], i32 6
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; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[SCEVGEP14]], align 2
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; CHECK-NEXT: [[TMP11:%.*]] = trunc i32 [[TMP10]] to i16
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; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.arm.smladx(i32 [[TMP10]], i32 [[TMP2]], i32 undef)
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; CHECK-NEXT: [[TMP13:%.*]] = sext i16 [[TMP11]] to i32
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; CHECK-NEXT: [[TMP14:%.*]] = lshr i32 [[TMP10]], 16
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; CHECK-NEXT: [[TMP15:%.*]] = trunc i32 [[TMP14]] to i16
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; CHECK-NEXT: [[TMP16:%.*]] = sext i16 [[TMP15]] to i32
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; CHECK-NEXT: [[CONV31:%.*]] = sext i16 [[TMP8]] to i32
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; CHECK-NEXT: [[TMP17:%.*]] = load i16, ptr [[INCDEC_PTR29]], align 2
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; CHECK-NEXT: [[CONV33:%.*]] = sext i16 [[TMP17]] to i32
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; CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[SCEVGEP14]], align 2
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; CHECK-NEXT: [[CONV39:%.*]] = sext i16 [[TMP18]] to i32
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; CHECK-NEXT: [[MUL_I287_NEG_NEG:%.*]] = mul nsw i32 [[TMP16]], [[TMP4]]
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; CHECK-NEXT: [[MUL_I283_NEG_NEG:%.*]] = mul nsw i32 [[TMP13]], [[TMP7]]
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; CHECK-NEXT: [[REASS_ADD408:%.*]] = add i32 undef, [[MUL_I287_NEG_NEG]]
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; CHECK-NEXT: [[REASS_ADD409:%.*]] = add i32 [[REASS_ADD408]], [[MUL_I283_NEG_NEG]]
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; CHECK-NEXT: br label [[FOR_BODY]]
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;
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entry:
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%incdec.ptr21 = getelementptr inbounds i16, ptr %a, i32 3
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%incdec.ptr29 = getelementptr inbounds i16, ptr %a, i32 4
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br label %for.body
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for.body:
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%0 = load i16, ptr %incdec.ptr21, align 2
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%conv25 = sext i16 %0 to i32
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%uglygep15 = getelementptr i8, ptr undef, i32 undef
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%scevgep17 = getelementptr i16, ptr %uglygep15, i32 7
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%1 = load i16, ptr %scevgep17, align 2
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%conv31 = sext i16 %1 to i32
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%2 = load i16, ptr %incdec.ptr29, align 2
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%conv33 = sext i16 %2 to i32
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%uglygep12 = getelementptr i8, ptr undef, i32 undef
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%scevgep14 = getelementptr i16, ptr %uglygep12, i32 6
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%3 = load i16, ptr %scevgep14, align 2
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%conv39 = sext i16 %3 to i32
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%mul.i287.neg.neg = mul nsw i32 %conv31, %conv25
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%mul.i283.neg.neg = mul nsw i32 %conv39, %conv33
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%reass.add408 = add i32 undef, %mul.i287.neg.neg
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%reass.add409 = add i32 %reass.add408, %mul.i283.neg.neg
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br label %for.body
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}
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define i32 @return(ptr %a, ptr %b, i32 %N) {
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; CHECK-LABEL: @return(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[INCDEC_PTR21:%.*]] = getelementptr inbounds i16, ptr [[A:%.*]], i32 3
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; CHECK-NEXT: [[INCDEC_PTR29:%.*]] = getelementptr inbounds i16, ptr [[A]], i32 4
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[N:%.*]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[ACC:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP12:%.*]], [[FOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[INCDEC_PTR21]], align 2
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[INCDEC_PTR21]], align 2
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; CHECK-NEXT: [[TMP3:%.*]] = trunc i32 [[TMP2]] to i16
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; CHECK-NEXT: [[TMP4:%.*]] = sext i16 [[TMP3]] to i32
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; CHECK-NEXT: [[TMP5:%.*]] = lshr i32 [[TMP2]], 16
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; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16
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; CHECK-NEXT: [[TMP7:%.*]] = sext i16 [[TMP6]] to i32
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; CHECK-NEXT: [[CONV25:%.*]] = sext i16 [[TMP0]] to i32
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; CHECK-NEXT: [[B_IDX:%.*]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[SCEVGEP17:%.*]] = getelementptr i16, ptr [[B:%.*]], i32 [[B_IDX]]
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; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i16, ptr [[B]], i32 [[IV]]
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; CHECK-NEXT: [[TMP8:%.*]] = load i16, ptr [[SCEVGEP17]], align 2
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; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[SCEVGEP14]], align 2
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; CHECK-NEXT: [[TMP11:%.*]] = trunc i32 [[TMP10]] to i16
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; CHECK-NEXT: [[TMP12]] = call i32 @llvm.arm.smladx(i32 [[TMP10]], i32 [[TMP2]], i32 [[ACC]])
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; CHECK-NEXT: [[TMP13:%.*]] = sext i16 [[TMP11]] to i32
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; CHECK-NEXT: [[TMP14:%.*]] = lshr i32 [[TMP10]], 16
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; CHECK-NEXT: [[TMP15:%.*]] = trunc i32 [[TMP14]] to i16
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; CHECK-NEXT: [[TMP16:%.*]] = sext i16 [[TMP15]] to i32
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; CHECK-NEXT: [[CONV31:%.*]] = sext i16 [[TMP8]] to i32
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; CHECK-NEXT: [[TMP17:%.*]] = load i16, ptr [[INCDEC_PTR29]], align 2
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; CHECK-NEXT: [[CONV33:%.*]] = sext i16 [[TMP17]] to i32
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; CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[SCEVGEP14]], align 2
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; CHECK-NEXT: [[CONV39:%.*]] = sext i16 [[TMP18]] to i32
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; CHECK-NEXT: [[MUL_I287_NEG_NEG:%.*]] = mul nsw i32 [[TMP16]], [[TMP4]]
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; CHECK-NEXT: [[MUL_I283_NEG_NEG:%.*]] = mul nsw i32 [[TMP13]], [[TMP7]]
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; CHECK-NEXT: [[REASS_ADD408:%.*]] = add i32 [[ACC]], [[MUL_I287_NEG_NEG]]
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; CHECK-NEXT: [[REASS_ADD409:%.*]] = add i32 [[REASS_ADD408]], [[MUL_I283_NEG_NEG]]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], -1
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[IV_NEXT]], 0
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 [[TMP12]]
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;
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entry:
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%incdec.ptr21 = getelementptr inbounds i16, ptr %a, i32 3
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%incdec.ptr29 = getelementptr inbounds i16, ptr %a, i32 4
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br label %for.body
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for.body:
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%iv = phi i32 [ %N, %entry ], [ %iv.next, %for.body ]
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%acc = phi i32 [ 0, %entry ], [ %reass.add409, %for.body ]
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%0 = load i16, ptr %incdec.ptr21, align 2
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%conv25 = sext i16 %0 to i32
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%b.idx = add nuw nsw i32 %iv, 1
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%scevgep17 = getelementptr i16, ptr %b, i32 %b.idx
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%scevgep14 = getelementptr i16, ptr %b, i32 %iv
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%1 = load i16, ptr %scevgep17, align 2
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%conv31 = sext i16 %1 to i32
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%2 = load i16, ptr %incdec.ptr29, align 2
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%conv33 = sext i16 %2 to i32
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%3 = load i16, ptr %scevgep14, align 2
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%conv39 = sext i16 %3 to i32
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%mul.i287.neg.neg = mul nsw i32 %conv31, %conv25
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%mul.i283.neg.neg = mul nsw i32 %conv39, %conv33
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%reass.add408 = add i32 %acc, %mul.i287.neg.neg
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%reass.add409 = add i32 %reass.add408, %mul.i283.neg.neg
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%iv.next = add nuw nsw i32 %iv, -1
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%cmp = icmp ne i32 %iv.next, 0
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br i1 %cmp, label %for.body, label %exit
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exit:
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ret i32 %reass.add409
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}
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