139 lines
4.2 KiB
LLVM
139 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm-eabi -mattr=+neon | FileCheck %s
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define <8 x i8> @vceqi8(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: vceqi8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vceq.i8 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, ptr %A
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%tmp2 = load <8 x i8>, ptr %B
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%tmp3 = icmp eq <8 x i8> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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define <4 x i16> @vceqi16(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: vceqi16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vceq.i16 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i16>, ptr %A
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%tmp2 = load <4 x i16>, ptr %B
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%tmp3 = icmp eq <4 x i16> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i16>
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ret <4 x i16> %tmp4
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}
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define <2 x i32> @vceqi32(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: vceqi32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vceq.i32 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x i32>, ptr %A
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%tmp2 = load <2 x i32>, ptr %B
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%tmp3 = icmp eq <2 x i32> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <2 x i32> @vceqf32(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: vceqf32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r1]
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; CHECK-NEXT: vldr d17, [r0]
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; CHECK-NEXT: vceq.f32 d16, d17, d16
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <2 x float>, ptr %A
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%tmp2 = load <2 x float>, ptr %B
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%tmp3 = fcmp oeq <2 x float> %tmp1, %tmp2
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%tmp4 = sext <2 x i1> %tmp3 to <2 x i32>
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ret <2 x i32> %tmp4
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}
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define <16 x i8> @vceqQi8(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: vceqQi8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vceq.i8 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <16 x i8>, ptr %A
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%tmp2 = load <16 x i8>, ptr %B
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%tmp3 = icmp eq <16 x i8> %tmp1, %tmp2
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%tmp4 = sext <16 x i1> %tmp3 to <16 x i8>
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ret <16 x i8> %tmp4
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}
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define <8 x i16> @vceqQi16(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: vceqQi16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vceq.i16 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i16>, ptr %A
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%tmp2 = load <8 x i16>, ptr %B
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%tmp3 = icmp eq <8 x i16> %tmp1, %tmp2
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i16>
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ret <8 x i16> %tmp4
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}
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define <4 x i32> @vceqQi32(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: vceqQi32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vceq.i32 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x i32>, ptr %A
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%tmp2 = load <4 x i32>, ptr %B
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%tmp3 = icmp eq <4 x i32> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <4 x i32> @vceqQf32(ptr %A, ptr %B) nounwind {
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; CHECK-LABEL: vceqQf32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
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; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
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; CHECK-NEXT: vceq.f32 q8, q9, q8
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <4 x float>, ptr %A
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%tmp2 = load <4 x float>, ptr %B
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%tmp3 = fcmp oeq <4 x float> %tmp1, %tmp2
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%tmp4 = sext <4 x i1> %tmp3 to <4 x i32>
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ret <4 x i32> %tmp4
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}
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define <8 x i8> @vceqi8Z(ptr %A) nounwind {
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; CHECK-LABEL: vceqi8Z:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: vldr d16, [r0]
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; CHECK-NEXT: vceq.i8 d16, d16, #0
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: mov pc, lr
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%tmp1 = load <8 x i8>, ptr %A
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%tmp3 = icmp eq <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
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%tmp4 = sext <8 x i1> %tmp3 to <8 x i8>
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ret <8 x i8> %tmp4
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}
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