bolt/deps/llvm-18.1.8/llvm/test/CodeGen/Hexagon/vect/vect-mul-v4i16.ll
2025-02-14 19:21:04 +01:00

10 lines
214 B
LLVM

; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: vmpyh
; CHECK: vmpyh
; CHECK: vtrunewh
define <4 x i16> @t_i4x16(<4 x i16> %a, <4 x i16> %b) nounwind {
entry:
%0 = mul <4 x i16> %a, %b
ret <4 x i16> %0
}