bolt/deps/llvm-18.1.8/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
2025-02-14 19:21:04 +01:00

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# RUN: not llc -mtriple=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
---
name: wrong_reg_class_frame_offset_reg
machineFunctionInfo:
frameOffsetReg: '$vgpr0'
# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
body: |
bb.0:
S_ENDPGM
...