86 lines
2.6 KiB
YAML
86 lines
2.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -o - %s -march=nvptx64 -mcpu=sm_35 -run-pass=branch-folder | FileCheck %s
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--- |
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; ModuleID = '/mnt/nas/asavonic/work/llvm/llvm/test/CodeGen/NVPTX/branch-fold.ll'
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source_filename = "/mnt/nas/asavonic/work/llvm/llvm/test/CodeGen/NVPTX/branch-fold.ll"
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target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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define ptx_kernel void @hoge() {
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bb:
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br i1 undef, label %bb1.preheader, label %bb4.preheader
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bb1.preheader: ; preds = %bb
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br label %bb1
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bb1: ; preds = %bb1.preheader, %bb1
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%lsr.iv = phi i64 [ undef, %bb1.preheader ], [ %lsr.iv.next, %bb1 ]
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%lsr.iv.next = add i64 %lsr.iv, 1
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%tmp3 = icmp sle i64 %lsr.iv.next, 0
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br i1 %tmp3, label %bb1, label %bb4.preheader
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bb4.preheader: ; preds = %bb1, %bb
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br label %bb4
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bb4: ; preds = %bb4.preheader, %bb4
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br label %bb4
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}
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...
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---
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name: hoge
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alignment: 1
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tracksRegLiveness: true
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registers:
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- { id: 0, class: int64regs }
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- { id: 1, class: int64regs }
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- { id: 2, class: int1regs }
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- { id: 3, class: int64regs }
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- { id: 4, class: int1regs }
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- { id: 5, class: int64regs }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: hoge
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; CHECK: bb.0.bb:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: CBranch undef %2:int1regs, %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1.bb1.preheader:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:int64regs = IMPLICIT_DEF
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.bb1:
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; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[ADDi64ri:%[0-9]+]]:int64regs = ADDi64ri [[ADDi64ri]], 1
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; CHECK-NEXT: [[SETP_s64ri:%[0-9]+]]:int1regs = SETP_s64ri [[ADDi64ri]], 1, 2
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; CHECK-NEXT: CBranch [[SETP_s64ri]], %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3.bb4:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: GOTO %bb.3
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bb.0.bb:
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successors: %bb.1, %bb.3
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CBranch undef %2:int1regs, %bb.3
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bb.1.bb1.preheader:
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%5:int64regs = IMPLICIT_DEF
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bb.2.bb1:
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successors: %bb.2(0x7c000000), %bb.3(0x04000000)
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%5:int64regs = ADDi64ri %5, 1
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%4:int1regs = SETP_s64ri %5, 1, 2
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CBranch %4, %bb.2
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bb.3.bb4:
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GOTO %bb.3
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...
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