330 lines
15 KiB
YAML
330 lines
15 KiB
YAML
# RUN: llc --verify-machineinstrs -mcpu=pwr9 -o - %s -run-pass=pipeliner -ppc-enable-pipeliner -pipeliner-register-pressure -pipeliner-max-mii=50 -pipeliner-ii-search-range=30 -pipeliner-max-stages=10 -debug-only=pipeliner 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# Check that if the register pressure is too high, the schedule is rejected, II is incremented, and scheduling continues.
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# The specific value of II is not important.
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# CHECK: Try to schedule with 21
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# CHECK: Can't schedule
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# CHECK: Try to schedule with 22
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# CHECK: Can't schedule
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# CHECK: Try to schedule with 23
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# CHECK: Rejected the schedule because of too high register pressure
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# CHECK: Try to schedule with 24
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# CHECK: Rejected the schedule because of too high register pressure
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# CHECK: Try to schedule with 25
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# CHECK: Rejected the schedule because of too high register pressure
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# CHECK: Try to schedule with 26
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# CHECK: Schedule Found? 1 (II=26)
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--- |
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; ModuleID = 'a.ll'
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source_filename = "a.c"
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target datalayout = "e-m:e-Fn32-i64:64-n32:64"
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target triple = "ppc64le"
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; Function Attrs: nofree nosync nounwind memory(argmem: read) uwtable
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define dso_local double @kernel(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef signext %n) local_unnamed_addr #0 {
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entry:
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%0 = load double, ptr %a, align 8, !tbaa !3
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%arrayidx1 = getelementptr inbounds double, ptr %a, i64 1
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%1 = load double, ptr %arrayidx1, align 8, !tbaa !3
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%cmp163 = icmp sgt i32 %n, 0
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br i1 %cmp163, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%wide.trip.count = zext i32 %n to i64
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%scevgep1 = getelementptr i8, ptr %b, i64 -8
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call void @llvm.set.loop.iterations.i64(i64 %wide.trip.count)
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br label %for.body
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for.cond.cleanup: ; preds = %for.body, %entry
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%res.0.lcssa = phi double [ 0.000000e+00, %entry ], [ %30, %for.body ]
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ret double %res.0.lcssa
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for.body: ; preds = %for.body, %for.body.preheader
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%res.0165 = phi double [ 0.000000e+00, %for.body.preheader ], [ %30, %for.body ]
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%2 = phi ptr [ %scevgep1, %for.body.preheader ], [ %3, %for.body ]
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%3 = getelementptr i8, ptr %2, i64 8
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%4 = load double, ptr %3, align 8, !tbaa !3
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%5 = tail call double @llvm.fmuladd.f64(double %0, double %4, double %0)
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%6 = tail call double @llvm.fmuladd.f64(double %5, double %4, double %5)
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%7 = tail call double @llvm.fmuladd.f64(double %6, double %4, double %6)
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%8 = tail call double @llvm.fmuladd.f64(double %7, double %4, double %7)
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%9 = tail call double @llvm.fmuladd.f64(double %8, double %4, double %8)
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%10 = tail call double @llvm.fmuladd.f64(double %9, double %4, double %9)
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%11 = tail call double @llvm.fmuladd.f64(double %10, double %4, double %10)
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%12 = tail call double @llvm.fmuladd.f64(double %11, double %4, double %11)
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%13 = tail call double @llvm.fmuladd.f64(double %12, double %4, double %12)
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%14 = tail call double @llvm.fmuladd.f64(double %13, double %4, double %13)
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%15 = tail call double @llvm.fmuladd.f64(double %14, double %4, double %14)
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%16 = tail call double @llvm.fmuladd.f64(double %15, double %4, double %15)
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%17 = tail call double @llvm.fmuladd.f64(double %16, double %4, double %16)
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%18 = tail call double @llvm.fmuladd.f64(double %17, double %4, double %17)
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%19 = tail call double @llvm.fmuladd.f64(double %18, double %4, double %18)
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%20 = tail call double @llvm.fmuladd.f64(double %19, double %4, double %19)
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%add = fadd double %19, %20
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%21 = tail call double @llvm.fmuladd.f64(double %20, double %4, double %add)
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%add35 = fadd double %12, %21
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%22 = tail call double @llvm.fmuladd.f64(double %5, double %4, double %add35)
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%add38 = fadd double %13, %22
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%23 = tail call double @llvm.fmuladd.f64(double %6, double %4, double %add38)
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%mul = fmul double %4, %7
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%mul46 = fmul double %mul, %14
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%24 = tail call double @llvm.fmuladd.f64(double %mul46, double %13, double %16)
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%mul50 = fmul double %4, %9
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%mul51 = fmul double %1, %mul50
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%25 = tail call double @llvm.fmuladd.f64(double %mul51, double %11, double %24)
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%add53 = fadd double %5, %25
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%add54 = fadd double %6, %add53
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%mul55 = fmul double %14, %16
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%mul56 = fmul double %mul55, %17
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%mul57 = fmul double %mul56, %18
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%26 = tail call double @llvm.fmuladd.f64(double %mul57, double %19, double %add54)
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%27 = tail call double @llvm.fmuladd.f64(double %10, double %1, double %26)
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%28 = tail call double @llvm.fmuladd.f64(double %8, double %6, double %27)
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%mul61 = fmul double %20, %21
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%mul62 = fmul double %mul61, %22
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%29 = tail call double @llvm.fmuladd.f64(double %mul62, double %23, double %28)
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%mul64 = fmul double %26, %29
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%mul65 = fmul double %24, %mul64
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%mul66 = fmul double %12, %mul65
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%30 = tail call double @llvm.fmuladd.f64(double %mul66, double %10, double %res.0165)
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%31 = call i1 @llvm.loop.decrement.i64(i64 1)
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br i1 %31, label %for.body, label %for.cond.cleanup, !llvm.loop !7
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}
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare double @llvm.fmuladd.f64(double, double, double) #1
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; Function Attrs: nocallback noduplicate nofree nosync nounwind willreturn
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declare void @llvm.set.loop.iterations.i64(i64) #2
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; Function Attrs: nocallback noduplicate nofree nosync nounwind willreturn
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declare i1 @llvm.loop.decrement.i64(i64) #2
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attributes #0 = { nofree nosync nounwind memory(argmem: read) uwtable "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crbits,+crypto,+direct-move,+extdiv,+htm,+isa-v206-instructions,+isa-v207-instructions,+isa-v30-instructions,+power8-vector,+power9-vector,+quadword-atomics,+vsx,-aix-small-local-exec-tls,-privileged,-rop-protect,-spe" }
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attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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attributes #2 = { nocallback noduplicate nofree nosync nounwind willreturn }
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!llvm.module.flags = !{!0, !1}
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!llvm.ident = !{!2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 7, !"uwtable", i32 2}
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!2 = !{!"clang version 18.0.0 (https://miratech-soft@dev.azure.com/miratech-soft/llvm/_git/llvm c8d01fb665fc5d9378100a6d92ebcd3be49be655)"}
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!3 = !{!4, !4, i64 0}
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!4 = !{!"double", !5, i64 0}
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!5 = !{!"omnipotent char", !6, i64 0}
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!6 = !{!"Simple C/C++ TBAA"}
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!7 = distinct !{!7, !8, !9}
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!8 = !{!"llvm.loop.mustprogress"}
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!9 = !{!"llvm.loop.unroll.disable"}
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...
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---
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name: kernel
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alignment: 16
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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callsEHReturn: false
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callsUnwindInit: false
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hasEHCatchret: false
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hasEHScopes: false
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hasEHFunclets: false
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isOutlined: false
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debugInstrRef: false
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failsVerification: false
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tracksDebugUserValues: false
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registers:
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- { id: 0, class: vsfrc, preferred-register: '' }
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- { id: 1, class: vsfrc, preferred-register: '' }
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- { id: 2, class: g8rc, preferred-register: '' }
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- { id: 3, class: vsfrc, preferred-register: '' }
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- { id: 4, class: vsfrc, preferred-register: '' }
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- { id: 5, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 6, class: g8rc, preferred-register: '' }
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- { id: 7, class: vsfrc, preferred-register: '' }
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- { id: 8, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 9, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 10, class: g8rc, preferred-register: '' }
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- { id: 11, class: gprc, preferred-register: '' }
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- { id: 12, class: vsfrc, preferred-register: '' }
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- { id: 13, class: crrc, preferred-register: '' }
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- { id: 14, class: vsfrc, preferred-register: '' }
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- { id: 15, class: g8rc, preferred-register: '' }
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- { id: 16, class: g8rc, preferred-register: '' }
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- { id: 17, class: g8rc, preferred-register: '' }
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- { id: 18, class: f8rc, preferred-register: '' }
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- { id: 19, class: g8rc_and_g8rc_nox0, preferred-register: '' }
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- { id: 20, class: vsfrc, preferred-register: '' }
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- { id: 21, class: vsfrc, preferred-register: '' }
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- { id: 22, class: vsfrc, preferred-register: '' }
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- { id: 23, class: vsfrc, preferred-register: '' }
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- { id: 24, class: vsfrc, preferred-register: '' }
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- { id: 25, class: vsfrc, preferred-register: '' }
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- { id: 26, class: vsfrc, preferred-register: '' }
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- { id: 27, class: vsfrc, preferred-register: '' }
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- { id: 28, class: vsfrc, preferred-register: '' }
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- { id: 29, class: vsfrc, preferred-register: '' }
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- { id: 30, class: vsfrc, preferred-register: '' }
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- { id: 31, class: vsfrc, preferred-register: '' }
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- { id: 32, class: vsfrc, preferred-register: '' }
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- { id: 33, class: vsfrc, preferred-register: '' }
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- { id: 34, class: vsfrc, preferred-register: '' }
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- { id: 35, class: vsfrc, preferred-register: '' }
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- { id: 36, class: vsfrc, preferred-register: '' }
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- { id: 37, class: vsfrc, preferred-register: '' }
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- { id: 38, class: vsfrc, preferred-register: '' }
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- { id: 39, class: vsfrc, preferred-register: '' }
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- { id: 40, class: vsfrc, preferred-register: '' }
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- { id: 41, class: vsfrc, preferred-register: '' }
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- { id: 42, class: vsfrc, preferred-register: '' }
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- { id: 43, class: vsfrc, preferred-register: '' }
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- { id: 44, class: vsfrc, preferred-register: '' }
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- { id: 45, class: vsfrc, preferred-register: '' }
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- { id: 46, class: vsfrc, preferred-register: '' }
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- { id: 47, class: vsfrc, preferred-register: '' }
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- { id: 48, class: vsfrc, preferred-register: '' }
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- { id: 49, class: vsfrc, preferred-register: '' }
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- { id: 50, class: vsfrc, preferred-register: '' }
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- { id: 51, class: vsfrc, preferred-register: '' }
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- { id: 52, class: vsfrc, preferred-register: '' }
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- { id: 53, class: vsfrc, preferred-register: '' }
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- { id: 54, class: vsfrc, preferred-register: '' }
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- { id: 55, class: vsfrc, preferred-register: '' }
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- { id: 56, class: vsfrc, preferred-register: '' }
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- { id: 57, class: vsfrc, preferred-register: '' }
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- { id: 58, class: vsfrc, preferred-register: '' }
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- { id: 59, class: vsfrc, preferred-register: '' }
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- { id: 60, class: vsfrc, preferred-register: '' }
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- { id: 61, class: vsfrc, preferred-register: '' }
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- { id: 62, class: crbitrc, preferred-register: '' }
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liveins:
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- { reg: '$x3', virtual-reg: '%8' }
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- { reg: '$x4', virtual-reg: '%9' }
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- { reg: '$x5', virtual-reg: '%10' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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functionContext: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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hasTailCall: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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entry_values: []
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.2(0x50000000), %bb.1(0x30000000)
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liveins: $x3, $x4, $x5
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%10:g8rc = COPY killed $x5
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%9:g8rc_and_g8rc_nox0 = COPY killed $x4
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%8:g8rc_and_g8rc_nox0 = COPY killed $x3
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%11:gprc = COPY killed %10.sub_32
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%13:crrc = CMPWI %11, 0
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BCC 44, killed %13, %bb.2
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bb.1:
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successors: %bb.3(0x80000000)
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%12:vsfrc = XXLXORdpz
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B %bb.3
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bb.2.for.body.preheader:
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successors: %bb.4(0x80000000)
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%0:vsfrc = DFLOADf64 0, %8 :: (load (s64) from %ir.a, !tbaa !3)
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%1:vsfrc = DFLOADf64 8, killed %8 :: (load (s64) from %ir.arrayidx1, !tbaa !3)
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%16:g8rc = IMPLICIT_DEF
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%15:g8rc = INSERT_SUBREG killed %16, killed %11, %subreg.sub_32
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%17:g8rc = RLDICL killed %15, 0, 32
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%2:g8rc = ADDI8 killed %9, -8
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MTCTR8loop killed %17, implicit-def dead $ctr8
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%14:vsfrc = XXLXORdpz
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B %bb.4
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bb.3.for.cond.cleanup:
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%3:vsfrc = PHI %12, %bb.1, %7, %bb.4
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$f1 = COPY killed %3
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BLR8 implicit $lr8, implicit $rm, implicit killed $f1
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bb.4.for.body:
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successors: %bb.4(0x7c000000), %bb.3(0x04000000)
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%4:vsfrc = PHI %14, %bb.2, %7, %bb.4
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%5:g8rc_and_g8rc_nox0 = PHI %2, %bb.2, %6, %bb.4
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%18:f8rc, %19:g8rc_and_g8rc_nox0 = LFDU 8, killed %5 :: (load (s64) from %ir.3, !tbaa !3)
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%6:g8rc = COPY killed %19
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%20:vsfrc = nofpexcept XSMADDADP %0, %0, %18, implicit $rm
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%21:vsfrc = nofpexcept XSMADDADP %20, %20, %18, implicit $rm
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%22:vsfrc = nofpexcept XSMADDADP %21, %21, %18, implicit $rm
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%23:vsfrc = nofpexcept XSMADDADP %22, %22, %18, implicit $rm
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%24:vsfrc = nofpexcept XSMADDADP %23, %23, %18, implicit $rm
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%25:vsfrc = nofpexcept XSMADDADP %24, %24, %18, implicit $rm
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%26:vsfrc = nofpexcept XSMADDADP %25, %25, %18, implicit $rm
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%27:vsfrc = nofpexcept XSMADDADP %26, %26, %18, implicit $rm
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%28:vsfrc = nofpexcept XSMADDADP %27, %27, %18, implicit $rm
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%29:vsfrc = nofpexcept XSMADDADP %28, %28, %18, implicit $rm
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%30:vsfrc = nofpexcept XSMADDADP %29, %29, %18, implicit $rm
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%31:vsfrc = nofpexcept XSMADDADP killed %30, %30, %18, implicit $rm
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%32:vsfrc = nofpexcept XSMADDADP %31, %31, %18, implicit $rm
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%33:vsfrc = nofpexcept XSMADDADP %32, %32, %18, implicit $rm
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%34:vsfrc = nofpexcept XSMADDADP %33, %33, %18, implicit $rm
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%35:vsfrc = nofpexcept XSMADDADP %34, %34, %18, implicit $rm
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%36:vsfrc = nofpexcept XSADDDP %34, %35, implicit $rm
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%37:vsfrc = nofpexcept XSMADDADP killed %36, %35, %18, implicit $rm
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%38:vsfrc = nofpexcept XSADDDP %27, %37, implicit $rm
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%39:vsfrc = nofpexcept XSMADDADP killed %38, %20, %18, implicit $rm
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%40:vsfrc = nofpexcept XSADDDP %28, %39, implicit $rm
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%41:vsfrc = nofpexcept XSMADDADP killed %40, %21, %18, implicit $rm
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%42:vsfrc = nofpexcept XSMULDP %18, killed %22, implicit $rm
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%43:vsfrc = nofpexcept XSMULDP killed %42, %29, implicit $rm
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%44:vsfrc = nofpexcept XSMADDADP %31, killed %43, killed %28, implicit $rm
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%45:vsfrc = nofpexcept XSMULDP killed %18, killed %24, implicit $rm
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%46:vsfrc = nofpexcept XSMULDP %1, killed %45, implicit $rm
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%47:vsfrc = nofpexcept XSMADDADP %44, killed %46, killed %26, implicit $rm
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%48:vsfrc = nofpexcept XSADDDP killed %20, killed %47, implicit $rm
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%49:vsfrc = nofpexcept XSADDDP %21, killed %48, implicit $rm
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%50:vsfrc = nofpexcept XSMULDP killed %29, killed %31, implicit $rm
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%51:vsfrc = nofpexcept XSMULDP killed %50, killed %32, implicit $rm
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%52:vsfrc = nofpexcept XSMULDP killed %51, killed %33, implicit $rm
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%53:vsfrc = nofpexcept XSMADDADP killed %49, killed %52, killed %34, implicit $rm
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%54:vsfrc = nofpexcept XSMADDADP %53, %25, %1, implicit $rm
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%55:vsfrc = nofpexcept XSMADDADP killed %54, killed %23, killed %21, implicit $rm
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%56:vsfrc = nofpexcept XSMULDP killed %35, killed %37, implicit $rm
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%57:vsfrc = nofpexcept XSMULDP killed %56, killed %39, implicit $rm
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%58:vsfrc = nofpexcept XSMADDADP killed %55, killed %57, killed %41, implicit $rm
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%59:vsfrc = nofpexcept XSMULDP killed %53, killed %58, implicit $rm
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%60:vsfrc = nofpexcept XSMULDP killed %44, killed %59, implicit $rm
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%61:vsfrc = nofpexcept XSMULDP killed %27, killed %60, implicit $rm
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%7:vsfrc = nofpexcept XSMADDADP killed %4, killed %61, killed %25, implicit $rm
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BDNZ8 %bb.4, implicit-def $ctr8, implicit $ctr8
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B %bb.3
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...
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