234 lines
6.4 KiB
YAML
234 lines
6.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=riscv64 -run-pass=regbankselect \
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# RUN: -disable-gisel-legality-check -simplify-mir -verify-machineinstrs %s \
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# RUN: -o - | FileCheck -check-prefix=RV64I %s
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---
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name: load_i8
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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; RV64I-LABEL: name: load_i8
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
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; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
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; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[LOAD]](s32)
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; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%3:_(s32) = G_LOAD %0(p0) :: (load (s8))
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%2:_(s64) = G_ANYEXT %3(s32)
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: load_i16
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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; RV64I-LABEL: name: load_i16
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
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; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
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; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[LOAD]](s32)
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; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%3:_(s32) = G_LOAD %0(p0) :: (load (s16))
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%2:_(s64) = G_ANYEXT %3(s32)
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: load_i32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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; RV64I-LABEL: name: load_i32
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
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; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
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; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[LOAD]](s32)
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; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%1:_(s32) = G_LOAD %0(p0) :: (load (s32))
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%2:_(s64) = G_ANYEXT %1(s32)
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: load_i64
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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; RV64I-LABEL: name: load_i64
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
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; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s64) = G_LOAD [[COPY]](p0) :: (load (s64))
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; RV64I-NEXT: $x10 = COPY [[LOAD]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%1:_(s64) = G_LOAD %0(p0) :: (load (s64))
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$x10 = COPY %1(s64)
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PseudoRET implicit $x10
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...
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---
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name: load_ptr
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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; RV64I-LABEL: name: load_ptr
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
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; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[COPY]](p0) :: (load (p0))
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; RV64I-NEXT: $x10 = COPY [[LOAD]](p0)
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%1:_(p0) = G_LOAD %0(p0) :: (load (p0))
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$x10 = COPY %1(p0)
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PseudoRET implicit $x10
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...
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---
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name: zextload_i8
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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%0:_(p0) = COPY $x10
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%3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
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%2:_(s64) = G_ANYEXT %3(s32)
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: zextload_i16
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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; RV64I-LABEL: name: zextload_i16
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
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; RV64I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
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; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[ZEXTLOAD]](s32)
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; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%3:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
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%2:_(s64) = G_ANYEXT %3(s32)
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: zextload_i32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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; RV64I-LABEL: name: zextload_i32
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
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; RV64I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s32))
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; RV64I-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%1:_(s64) = G_ZEXTLOAD %0(p0) :: (load (s32))
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$x10 = COPY %1(s64)
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PseudoRET implicit $x10
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...
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---
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name: sextload_i8
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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%0:_(p0) = COPY $x10
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%3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
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%2:_(s64) = G_ANYEXT %3(s32)
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: sextload_i16
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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; RV64I-LABEL: name: sextload_i16
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
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; RV64I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
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; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[SEXTLOAD]](s32)
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; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%3:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
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%2:_(s64) = G_ANYEXT %3(s32)
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$x10 = COPY %2(s64)
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PseudoRET implicit $x10
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...
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---
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name: sextload_i32
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10
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; RV64I-LABEL: name: sextload_i32
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; RV64I: liveins: $x10
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; RV64I-NEXT: {{ $}}
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; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
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; RV64I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s64) = G_SEXTLOAD [[COPY]](p0) :: (load (s32))
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; RV64I-NEXT: $x10 = COPY [[SEXTLOAD]](s64)
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; RV64I-NEXT: PseudoRET implicit $x10
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%0:_(p0) = COPY $x10
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%1:_(s64) = G_SEXTLOAD %0(p0) :: (load (s32))
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$x10 = COPY %1(s64)
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PseudoRET implicit $x10
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...
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