87 lines
3.3 KiB
YAML
87 lines
3.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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# RUN: llc %s -o - -mtriple=riscv64 -mattr=+f -run-pass=machine-combiner \
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# RUN: -verify-machineinstrs | FileCheck %s
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--- |
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source_filename = "test.ll"
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
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target triple = "riscv64"
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define void @foo(ptr %0, ptr %1, float %2, float %3, ptr %4, ptr %5) #0 {
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%7 = load float, ptr %0, align 4
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%8 = load float, ptr %1, align 4
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%9 = fmul fast float %8, %7
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%10 = fadd fast float %9, %2
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store float %10, ptr %4, align 4
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%11 = fsub fast float %3, %9
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store float %11, ptr %5, align 4
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ret void
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}
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attributes #0 = { "target-features"="+f" }
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...
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---
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name: foo
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: gpr }
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- { id: 2, class: fpr32 }
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- { id: 3, class: fpr32 }
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- { id: 4, class: gpr }
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- { id: 5, class: gpr }
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- { id: 6, class: fpr32 }
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- { id: 7, class: fpr32 }
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- { id: 8, class: fpr32 }
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- { id: 9, class: fpr32 }
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- { id: 10, class: fpr32 }
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liveins:
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- { reg: '$x10', virtual-reg: '%0' }
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- { reg: '$x11', virtual-reg: '%1' }
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- { reg: '$f10_f', virtual-reg: '%2' }
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- { reg: '$f11_f', virtual-reg: '%3' }
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- { reg: '$x12', virtual-reg: '%4' }
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- { reg: '$x13', virtual-reg: '%5' }
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frameInfo:
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maxAlignment: 1
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machineFunctionInfo:
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varArgsFrameIndex: 0
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varArgsSaveSize: 0
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body: |
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bb.0 (%ir-block.6):
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liveins: $x10, $x11, $f10_f, $f11_f, $x12, $x13
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; CHECK-LABEL: name: foo
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; CHECK: liveins: $x10, $x11, $f10_f, $f11_f, $x12, $x13
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f11_f
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $f10_f
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[FLW:%[0-9]+]]:fpr32 = FLW [[COPY5]], 0 :: (load (s32) from %ir.0)
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; CHECK-NEXT: [[FLW1:%[0-9]+]]:fpr32 = FLW [[COPY4]], 0 :: (load (s32) from %ir.1)
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; CHECK-NEXT: [[FMADD_S:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMADD_S [[FLW1]], [[FLW]], [[COPY3]], 7, implicit $frm
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; CHECK-NEXT: FSW killed [[FMADD_S]], [[COPY1]], 0 :: (store (s32) into %ir.4)
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; CHECK-NEXT: [[FNMSUB_S:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FNMSUB_S [[FLW1]], [[FLW]], [[COPY2]], 7, implicit $frm
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; CHECK-NEXT: FSW killed [[FNMSUB_S]], [[COPY]], 0 :: (store (s32) into %ir.5)
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; CHECK-NEXT: PseudoRET
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%5:gpr = COPY $x13
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%4:gpr = COPY $x12
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%3:fpr32 = COPY $f11_f
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%2:fpr32 = COPY $f10_f
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%1:gpr = COPY $x11
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%0:gpr = COPY $x10
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%6:fpr32 = FLW %0, 0 :: (load (s32) from %ir.0)
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%7:fpr32 = FLW %1, 0 :: (load (s32) from %ir.1)
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%8:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FMUL_S killed %7, killed %6, 7, implicit $frm
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%9:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FADD_S %8, %2, 7, implicit $frm
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FSW killed %9, %4, 0 :: (store (s32) into %ir.4)
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%10:fpr32 = nnan ninf nsz arcp contract afn reassoc nofpexcept FSUB_S %3, %8, 7, implicit $frm
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FSW killed %10, %5, 0 :: (store (s32) into %ir.5)
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PseudoRET
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...
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