bolt/deps/llvm-18.1.8/llvm/test/CodeGen/RISCV/rv64zknd-intrinsic.ll
2025-02-14 19:21:04 +01:00

36 lines
1 KiB
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+zknd -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZKND
declare i64 @llvm.riscv.aes64ds(i64, i64);
define i64 @aes64ds(i64 %a, i64 %b) nounwind {
; RV64ZKND-LABEL: aes64ds:
; RV64ZKND: # %bb.0:
; RV64ZKND-NEXT: aes64ds a0, a0, a1
; RV64ZKND-NEXT: ret
%val = call i64 @llvm.riscv.aes64ds(i64 %a, i64 %b)
ret i64 %val
}
declare i64 @llvm.riscv.aes64dsm(i64, i64);
define i64 @aes64dsm(i64 %a, i64 %b) nounwind {
; RV64ZKND-LABEL: aes64dsm:
; RV64ZKND: # %bb.0:
; RV64ZKND-NEXT: aes64dsm a0, a0, a1
; RV64ZKND-NEXT: ret
%val = call i64 @llvm.riscv.aes64dsm(i64 %a, i64 %b)
ret i64 %val
}
declare i64 @llvm.riscv.aes64im(i64);
define i64 @aes64im(i64 %a) nounwind {
; RV64ZKND-LABEL: aes64im:
; RV64ZKND: # %bb.0:
; RV64ZKND-NEXT: aes64im a0, a0
; RV64ZKND-NEXT: ret
%val = call i64 @llvm.riscv.aes64im(i64 %a)
ret i64 %val
}