184 lines
5.2 KiB
LLVM
184 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zve32f,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zve32f,+zvl128b -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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; Test that limiting ELEN through zve32 scalarizes elements larger than 32 bits
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; and disables some fractional LMULs.
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; This should use LMUL=1.
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define void @add_v4i32(ptr %x, ptr %y) {
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; CHECK-LABEL: add_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vle32.v v9, (a1)
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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%a = load <4 x i32>, ptr %x
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%b = load <4 x i32>, ptr %y
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%c = add <4 x i32> %a, %b
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store <4 x i32> %c, ptr %x
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ret void
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}
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; i64 vectors should be scalarized
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define void @add_v2i64(ptr %x, ptr %y) {
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; RV32-LABEL: add_v2i64:
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; RV32: # %bb.0:
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; RV32-NEXT: lw a2, 8(a0)
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; RV32-NEXT: lw a3, 12(a0)
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; RV32-NEXT: lw a4, 0(a0)
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; RV32-NEXT: lw a5, 4(a0)
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; RV32-NEXT: lw a6, 4(a1)
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; RV32-NEXT: lw a7, 0(a1)
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; RV32-NEXT: lw t0, 8(a1)
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; RV32-NEXT: lw a1, 12(a1)
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; RV32-NEXT: add a5, a5, a6
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; RV32-NEXT: add a7, a4, a7
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; RV32-NEXT: sltu a4, a7, a4
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; RV32-NEXT: add a4, a5, a4
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; RV32-NEXT: add a1, a3, a1
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; RV32-NEXT: add t0, a2, t0
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; RV32-NEXT: sltu a2, t0, a2
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; RV32-NEXT: add a1, a1, a2
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; RV32-NEXT: sw t0, 8(a0)
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; RV32-NEXT: sw a7, 0(a0)
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; RV32-NEXT: sw a1, 12(a0)
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; RV32-NEXT: sw a4, 4(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: add_v2i64:
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; RV64: # %bb.0:
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; RV64-NEXT: ld a2, 8(a0)
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; RV64-NEXT: ld a3, 0(a0)
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; RV64-NEXT: ld a4, 0(a1)
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; RV64-NEXT: ld a1, 8(a1)
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; RV64-NEXT: add a3, a3, a4
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; RV64-NEXT: add a1, a2, a1
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; RV64-NEXT: sd a1, 8(a0)
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; RV64-NEXT: sd a3, 0(a0)
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; RV64-NEXT: ret
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%a = load <2 x i64>, ptr %x
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%b = load <2 x i64>, ptr %y
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%c = add <2 x i64> %a, %b
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store <2 x i64> %c, ptr %x
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ret void
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}
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; This should use LMUL=1 becuase there are no fractional i32 LMULs with ELEN=32
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define void @add_v2i32(ptr %x, ptr %y) {
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; CHECK-LABEL: add_v2i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vle32.v v9, (a1)
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; CHECK-NEXT: vadd.vv v8, v8, v9
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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%a = load <2 x i32>, ptr %x
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%b = load <2 x i32>, ptr %y
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%c = add <2 x i32> %a, %b
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store <2 x i32> %c, ptr %x
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ret void
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}
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; i64 vectors should be scalarized
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define void @add_v1i64(ptr %x, ptr %y) {
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; RV32-LABEL: add_v1i64:
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; RV32: # %bb.0:
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; RV32-NEXT: lw a2, 0(a0)
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; RV32-NEXT: lw a3, 4(a0)
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; RV32-NEXT: lw a4, 4(a1)
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; RV32-NEXT: lw a1, 0(a1)
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; RV32-NEXT: add a3, a3, a4
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; RV32-NEXT: add a1, a2, a1
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; RV32-NEXT: sltu a2, a1, a2
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; RV32-NEXT: add a2, a3, a2
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; RV32-NEXT: sw a1, 0(a0)
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; RV32-NEXT: sw a2, 4(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: add_v1i64:
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; RV64: # %bb.0:
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; RV64-NEXT: ld a2, 0(a0)
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; RV64-NEXT: ld a1, 0(a1)
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; RV64-NEXT: add a1, a2, a1
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; RV64-NEXT: sd a1, 0(a0)
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; RV64-NEXT: ret
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%a = load <1 x i64>, ptr %x
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%b = load <1 x i64>, ptr %y
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%c = add <1 x i64> %a, %b
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store <1 x i64> %c, ptr %x
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ret void
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}
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; This should use LMUL=1.
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define void @fadd_v4f32(ptr %x, ptr %y) {
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; CHECK-LABEL: fadd_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vle32.v v9, (a1)
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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%a = load <4 x float>, ptr %x
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%b = load <4 x float>, ptr %y
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%c = fadd <4 x float> %a, %b
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store <4 x float> %c, ptr %x
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ret void
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}
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; double vectors should be scalarized
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define void @fadd_v2f64(ptr %x, ptr %y) {
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; CHECK-LABEL: fadd_v2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fld fa5, 8(a0)
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; CHECK-NEXT: fld fa4, 0(a0)
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; CHECK-NEXT: fld fa3, 0(a1)
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; CHECK-NEXT: fld fa2, 8(a1)
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; CHECK-NEXT: fadd.d fa4, fa4, fa3
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; CHECK-NEXT: fadd.d fa5, fa5, fa2
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; CHECK-NEXT: fsd fa5, 8(a0)
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; CHECK-NEXT: fsd fa4, 0(a0)
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; CHECK-NEXT: ret
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%a = load <2 x double>, ptr %x
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%b = load <2 x double>, ptr %y
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%c = fadd <2 x double> %a, %b
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store <2 x double> %c, ptr %x
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ret void
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}
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; This should use LMUL=1 becuase there are no fractional float LMULs with ELEN=32
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define void @fadd_v2f32(ptr %x, ptr %y) {
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; CHECK-LABEL: fadd_v2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vle32.v v9, (a1)
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; CHECK-NEXT: vfadd.vv v8, v8, v9
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; CHECK-NEXT: vse32.v v8, (a0)
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; CHECK-NEXT: ret
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%a = load <2 x float>, ptr %x
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%b = load <2 x float>, ptr %y
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%c = fadd <2 x float> %a, %b
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store <2 x float> %c, ptr %x
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ret void
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}
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; double vectors should be scalarized
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define void @fadd_v1f64(ptr %x, ptr %y) {
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; CHECK-LABEL: fadd_v1f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fld fa5, 0(a0)
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; CHECK-NEXT: fld fa4, 0(a1)
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; CHECK-NEXT: fadd.d fa5, fa5, fa4
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; CHECK-NEXT: fsd fa5, 0(a0)
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; CHECK-NEXT: ret
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%a = load <1 x double>, ptr %x
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%b = load <1 x double>, ptr %y
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%c = fadd <1 x double> %a, %b
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store <1 x double> %c, ptr %x
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ret void
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}
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