1594 lines
53 KiB
LLVM
1594 lines
53 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s
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declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>)
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define half @vreduce_fadd_v1f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_fadd_v1f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fadd.h fa0, fa0, fa5
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; CHECK-NEXT: ret
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%v = load <1 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v1f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_ord_fadd_v1f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vfredosum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <1 x half>, ptr %x
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%red = call half @llvm.vector.reduce.fadd.v1f16(half %s, <1 x half> %v)
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ret half %red
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}
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declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>)
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define half @vreduce_fadd_v2f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_fadd_v2f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vfredusum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <2 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v2f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_ord_fadd_v2f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vfredosum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <2 x half>, ptr %x
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%red = call half @llvm.vector.reduce.fadd.v2f16(half %s, <2 x half> %v)
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ret half %red
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}
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declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
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define half @vreduce_fadd_v4f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_fadd_v4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vfredusum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <4 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v4f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_ord_fadd_v4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vfredosum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <4 x half>, ptr %x
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%red = call half @llvm.vector.reduce.fadd.v4f16(half %s, <4 x half> %v)
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ret half %red
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}
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declare half @llvm.vector.reduce.fadd.v8f16(half, <8 x half>)
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define half @vreduce_fadd_v8f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_fadd_v8f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vfredusum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <8 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v8f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_ord_fadd_v8f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vfredosum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <8 x half>, ptr %x
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%red = call half @llvm.vector.reduce.fadd.v8f16(half %s, <8 x half> %v)
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ret half %red
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}
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declare half @llvm.vector.reduce.fadd.v16f16(half, <16 x half>)
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define half @vreduce_fadd_v16f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_fadd_v16f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v10, fa0
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; CHECK-NEXT: vfredusum.vs v8, v8, v10
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <16 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v16f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_ord_fadd_v16f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v10, fa0
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; CHECK-NEXT: vfredosum.vs v8, v8, v10
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <16 x half>, ptr %x
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%red = call half @llvm.vector.reduce.fadd.v16f16(half %s, <16 x half> %v)
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ret half %red
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}
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declare half @llvm.vector.reduce.fadd.v32f16(half, <32 x half>)
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define half @vreduce_fadd_v32f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_fadd_v32f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a1, 32
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; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v12, fa0
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; CHECK-NEXT: vfredusum.vs v8, v8, v12
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <32 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v32f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_ord_fadd_v32f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a1, 32
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; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v12, fa0
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; CHECK-NEXT: vfredosum.vs v8, v8, v12
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <32 x half>, ptr %x
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%red = call half @llvm.vector.reduce.fadd.v32f16(half %s, <32 x half> %v)
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ret half %red
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}
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declare half @llvm.vector.reduce.fadd.v64f16(half, <64 x half>)
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define half @vreduce_fadd_v64f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_fadd_v64f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a1, 64
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; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v16, fa0
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; CHECK-NEXT: vfredusum.vs v8, v8, v16
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <64 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v64f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_ord_fadd_v64f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a1, 64
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; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v16, fa0
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; CHECK-NEXT: vfredosum.vs v8, v8, v16
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <64 x half>, ptr %x
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%red = call half @llvm.vector.reduce.fadd.v64f16(half %s, <64 x half> %v)
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ret half %red
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}
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declare half @llvm.vector.reduce.fadd.v128f16(half, <128 x half>)
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define half @vreduce_fadd_v128f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_fadd_v128f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a1, 64
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; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: addi a0, a0, 128
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; CHECK-NEXT: vle16.v v16, (a0)
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; CHECK-NEXT: vfadd.vv v8, v8, v16
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; CHECK-NEXT: vfmv.s.f v16, fa0
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; CHECK-NEXT: vfredusum.vs v8, v8, v16
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <128 x half>, ptr %x
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%red = call reassoc half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
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ret half %red
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}
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define half @vreduce_ord_fadd_v128f16(ptr %x, half %s) {
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; CHECK-LABEL: vreduce_ord_fadd_v128f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi a1, a0, 128
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; CHECK-NEXT: li a2, 64
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; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vle16.v v16, (a1)
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; CHECK-NEXT: vfmv.s.f v24, fa0
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; CHECK-NEXT: vfredosum.vs v8, v8, v24
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; CHECK-NEXT: vfredosum.vs v8, v16, v8
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <128 x half>, ptr %x
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%red = call half @llvm.vector.reduce.fadd.v128f16(half %s, <128 x half> %v)
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ret half %red
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}
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declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>)
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define float @vreduce_fadd_v1f32(ptr %x, float %s) {
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; CHECK-LABEL: vreduce_fadd_v1f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fadd.s fa0, fa0, fa5
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; CHECK-NEXT: ret
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%v = load <1 x float>, ptr %x
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%red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
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ret float %red
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}
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define float @vreduce_ord_fadd_v1f32(ptr %x, float %s) {
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; CHECK-LABEL: vreduce_ord_fadd_v1f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vfredosum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <1 x float>, ptr %x
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%red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %v)
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ret float %red
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}
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define float @vreduce_fwadd_v1f32(ptr %x, float %s) {
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; CHECK-LABEL: vreduce_fwadd_v1f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfwcvt.f.f.v v9, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; CHECK-NEXT: vfmv.f.s fa5, v9
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; CHECK-NEXT: fadd.s fa0, fa0, fa5
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; CHECK-NEXT: ret
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%v = load <1 x half>, ptr %x
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%e = fpext <1 x half> %v to <1 x float>
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%red = call reassoc float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %e)
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ret float %red
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}
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define float @vreduce_ord_fwadd_v1f32(ptr %x, float %s) {
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; CHECK-LABEL: vreduce_ord_fwadd_v1f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vfwredosum.vs v8, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <1 x half>, ptr %x
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%e = fpext <1 x half> %v to <1 x float>
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%red = call float @llvm.vector.reduce.fadd.v1f32(float %s, <1 x float> %e)
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ret float %red
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}
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declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>)
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define float @vreduce_fadd_v2f32(ptr %x, float %s) {
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; CHECK-LABEL: vreduce_fadd_v2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vfredusum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <2 x float>, ptr %x
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%red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
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ret float %red
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}
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define float @vreduce_ord_fadd_v2f32(ptr %x, float %s) {
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; CHECK-LABEL: vreduce_ord_fadd_v2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vfredosum.vs v8, v8, v9
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <2 x float>, ptr %x
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%red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %v)
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ret float %red
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}
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define float @vreduce_fwadd_v2f32(ptr %x, float %s) {
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; CHECK-LABEL: vreduce_fwadd_v2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vfmv.s.f v9, fa0
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; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; CHECK-NEXT: vfwredusum.vs v8, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <2 x half>, ptr %x
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%e = fpext <2 x half> %v to <2 x float>
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%red = call reassoc float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %e)
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ret float %red
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}
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define float @vreduce_ord_fwadd_v2f32(ptr %x, float %s) {
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|
; CHECK-LABEL: vreduce_ord_fwadd_v2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x half>, ptr %x
|
|
%e = fpext <2 x half> %v to <2 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v2f32(float %s, <2 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
declare float @llvm.vector.reduce.fadd.v4f32(float, <4 x float>)
|
|
|
|
define float @vreduce_fadd_v4f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v4f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v4f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%e = fpext <4 x half> %v to <4 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v4f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%e = fpext <4 x half> %v to <4 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>)
|
|
|
|
define float @vreduce_fadd_v8f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v8f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v8f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v8f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v8f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v8f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x half>, ptr %x
|
|
%e = fpext <8 x half> %v to <8 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v8f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v8f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x half>, ptr %x
|
|
%e = fpext <8 x half> %v to <8 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v8f32(float %s, <8 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
declare float @llvm.vector.reduce.fadd.v16f32(float, <16 x float>)
|
|
|
|
define float @vreduce_fadd_v16f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v16f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v12
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v16f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v16f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v12
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v16f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v16f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v10
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x half>, ptr %x
|
|
%e = fpext <16 x half> %v to <16 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v16f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v16f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v10
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x half>, ptr %x
|
|
%e = fpext <16 x half> %v to <16 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v16f32(float %s, <16 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
declare float @llvm.vector.reduce.fadd.v32f32(float, <32 x float>)
|
|
|
|
define float @vreduce_fadd_v32f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v32f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v32f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v32f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v32f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v32f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v12
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x half>, ptr %x
|
|
%e = fpext <32 x half> %v to <32 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v32f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v32f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v12
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x half>, ptr %x
|
|
%e = fpext <32 x half> %v to <32 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v32f32(float %s, <32 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
declare float @llvm.vector.reduce.fadd.v64f32(float, <64 x float>)
|
|
|
|
define float @vreduce_fadd_v64f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v64f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle32.v v16, (a0)
|
|
; CHECK-NEXT: vfadd.vv v8, v8, v16
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x float>, ptr %x
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fadd_v64f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v64f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi a1, a0, 128
|
|
; CHECK-NEXT: li a2, 32
|
|
; CHECK-NEXT: vsetvli zero, a2, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vle32.v v16, (a1)
|
|
; CHECK-NEXT: vfmv.s.f v24, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v24
|
|
; CHECK-NEXT: vfredosum.vs v8, v16, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fwadd_v64f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v64f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 64
|
|
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: li a0, 32
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; CHECK-NEXT: vslidedown.vx v16, v8, a0
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; CHECK-NEXT: vfwadd.vv v24, v8, v16
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.s.f v8, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v24, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%e = fpext <64 x half> %v to <64 x float>
|
|
%red = call reassoc float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_ord_fwadd_v64f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v64f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 64
|
|
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: li a0, 32
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
|
|
; CHECK-NEXT: vslidedown.vx v16, v8, a0
|
|
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v12
|
|
; CHECK-NEXT: vfwredosum.vs v8, v16, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <64 x half>, ptr %x
|
|
%e = fpext <64 x half> %v to <64 x float>
|
|
%red = call float @llvm.vector.reduce.fadd.v64f32(float %s, <64 x float> %e)
|
|
ret float %red
|
|
}
|
|
|
|
declare double @llvm.vector.reduce.fadd.v1f64(double, <1 x double>)
|
|
|
|
define double @vreduce_fadd_v1f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v1f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.f.s fa5, v8
|
|
; CHECK-NEXT: fadd.d fa0, fa0, fa5
|
|
; CHECK-NEXT: ret
|
|
%v = load <1 x double>, ptr %x
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v)
|
|
ret double %red
|
|
}
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|
|
|
define double @vreduce_ord_fadd_v1f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v1f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
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|
%v = load <1 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %v)
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|
ret double %red
|
|
}
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|
|
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define double @vreduce_fwadd_v1f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v1f64:
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|
; CHECK: # %bb.0:
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|
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfwcvt.f.f.v v9, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa5, v9
|
|
; CHECK-NEXT: fadd.d fa0, fa0, fa5
|
|
; CHECK-NEXT: ret
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%v = load <1 x float>, ptr %x
|
|
%e = fpext <1 x float> %v to <1 x double>
|
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%red = call reassoc double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %e)
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|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v1f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v1f64:
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|
; CHECK: # %bb.0:
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|
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
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|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
|
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; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
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|
; CHECK-NEXT: vfmv.f.s fa0, v8
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|
; CHECK-NEXT: ret
|
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%v = load <1 x float>, ptr %x
|
|
%e = fpext <1 x float> %v to <1 x double>
|
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%red = call double @llvm.vector.reduce.fadd.v1f64(double %s, <1 x double> %e)
|
|
ret double %red
|
|
}
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declare double @llvm.vector.reduce.fadd.v2f64(double, <2 x double>)
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|
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define double @vreduce_fadd_v2f64(ptr %x, double %s) {
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; CHECK-LABEL: vreduce_fadd_v2f64:
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|
; CHECK: # %bb.0:
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|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fadd_v2f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fwadd_v2f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%e = fpext <2 x float> %v to <2 x double>
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v2f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%e = fpext <2 x float> %v to <2 x double>
|
|
%red = call double @llvm.vector.reduce.fadd.v2f64(double %s, <2 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
declare double @llvm.vector.reduce.fadd.v4f64(double, <4 x double>)
|
|
|
|
define double @vreduce_fadd_v4f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fadd_v4f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v10
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fwadd_v4f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%e = fpext <4 x float> %v to <4 x double>
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v4f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v9
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%e = fpext <4 x float> %v to <4 x double>
|
|
%red = call double @llvm.vector.reduce.fadd.v4f64(double %s, <4 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
declare double @llvm.vector.reduce.fadd.v8f64(double, <8 x double>)
|
|
|
|
define double @vreduce_fadd_v8f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v8f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v12
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x double>, ptr %x
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fadd_v8f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v8f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v12
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fwadd_v8f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v8f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v10
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%e = fpext <8 x float> %v to <8 x double>
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v8f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v8f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v10, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v10
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <8 x float>, ptr %x
|
|
%e = fpext <8 x float> %v to <8 x double>
|
|
%red = call double @llvm.vector.reduce.fadd.v8f64(double %s, <8 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
declare double @llvm.vector.reduce.fadd.v16f64(double, <16 x double>)
|
|
|
|
define double @vreduce_fadd_v16f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v16f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x double>, ptr %x
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fadd_v16f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v16f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fwadd_v16f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v16f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfwredusum.vs v8, v8, v12
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%e = fpext <16 x float> %v to <16 x double>
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v16f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v16f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v12
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <16 x float>, ptr %x
|
|
%e = fpext <16 x float> %v to <16 x double>
|
|
%red = call double @llvm.vector.reduce.fadd.v16f64(double %s, <16 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
declare double @llvm.vector.reduce.fadd.v32f64(double, <32 x double>)
|
|
|
|
define double @vreduce_fadd_v32f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fadd_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle64.v v16, (a0)
|
|
; CHECK-NEXT: vfadd.vv v8, v8, v16
|
|
; CHECK-NEXT: vfmv.s.f v16, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v16
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fadd_v32f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fadd_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: addi a1, a0, 128
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vle64.v v16, (a1)
|
|
; CHECK-NEXT: vfmv.s.f v24, fa0
|
|
; CHECK-NEXT: vfredosum.vs v8, v8, v24
|
|
; CHECK-NEXT: vfredosum.vs v8, v16, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fwadd_v32f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_fwadd_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
|
|
; CHECK-NEXT: vslidedown.vi v16, v8, 16
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfwadd.vv v24, v8, v16
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.s.f v8, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v24, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%e = fpext <32 x float> %v to <32 x double>
|
|
%red = call reassoc double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_ord_fwadd_v32f64(ptr %x, double %s) {
|
|
; CHECK-LABEL: vreduce_ord_fwadd_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
|
|
; CHECK-NEXT: vslidedown.vi v16, v8, 16
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m1, ta, ma
|
|
; CHECK-NEXT: vfmv.s.f v12, fa0
|
|
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
|
|
; CHECK-NEXT: vfwredosum.vs v8, v8, v12
|
|
; CHECK-NEXT: vfwredosum.vs v8, v16, v8
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x float>, ptr %x
|
|
%e = fpext <32 x float> %v to <32 x double>
|
|
%red = call double @llvm.vector.reduce.fadd.v32f64(double %s, <32 x double> %e)
|
|
ret double %red
|
|
}
|
|
|
|
declare half @llvm.vector.reduce.fmin.v2f16(<2 x half>)
|
|
|
|
define half @vreduce_fmin_v2f16(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v2f16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmin.v2f16(<2 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
declare half @llvm.vector.reduce.fmin.v4f16(<4 x half>)
|
|
|
|
define half @vreduce_fmin_v4f16(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmin_v4f16_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f16_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call nnan half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmin_v4f16_nonans_noinfs(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f16_nonans_noinfs:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call nnan ninf half @llvm.vector.reduce.fmin.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
declare half @llvm.vector.reduce.fmin.v128f16(<128 x half>)
|
|
|
|
define half @vreduce_fmin_v128f16(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v128f16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 64
|
|
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle16.v v16, (a0)
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <128 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmin.v128f16(<128 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)
|
|
|
|
define float @vreduce_fmin_v2f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmin.v2f32(<2 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)
|
|
|
|
define float @vreduce_fmin_v4f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmin_v4f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmin_v4f32_nonans_noinfs(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f32_nonans_noinfs:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call nnan ninf float @llvm.vector.reduce.fmin.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
declare float @llvm.vector.reduce.fmin.v128f32(<128 x float>)
|
|
|
|
define float @vreduce_fmin_v128f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v128f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 32
|
|
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: addi a1, a0, 384
|
|
; CHECK-NEXT: vle32.v v16, (a1)
|
|
; CHECK-NEXT: addi a1, a0, 256
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle32.v v24, (a0)
|
|
; CHECK-NEXT: vle32.v v0, (a1)
|
|
; CHECK-NEXT: vfmin.vv v16, v24, v16
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v0
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <128 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmin.v128f32(<128 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)
|
|
|
|
define double @vreduce_fmin_v2f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmin.v2f64(<2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
declare double @llvm.vector.reduce.fmin.v4f64(<4 x double>)
|
|
|
|
define double @vreduce_fmin_v4f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmin_v4f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmin_v4f64_nonans_noinfs(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v4f64_nonans_noinfs:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call nnan ninf double @llvm.vector.reduce.fmin.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
declare double @llvm.vector.reduce.fmin.v32f64(<32 x double>)
|
|
|
|
define double @vreduce_fmin_v32f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmin_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle64.v v16, (a0)
|
|
; CHECK-NEXT: vfmin.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmin.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmin.v32f64(<32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
declare half @llvm.vector.reduce.fmax.v2f16(<2 x half>)
|
|
|
|
define half @vreduce_fmax_v2f16(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v2f16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmax.v2f16(<2 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
declare half @llvm.vector.reduce.fmax.v4f16(<4 x half>)
|
|
|
|
define half @vreduce_fmax_v4f16(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmax_v4f16_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f16_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call nnan half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
define half @vreduce_fmax_v4f16_nonans_noinfs(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f16_nonans_noinfs:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x half>, ptr %x
|
|
%red = call nnan ninf half @llvm.vector.reduce.fmax.v4f16(<4 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
declare half @llvm.vector.reduce.fmax.v128f16(<128 x half>)
|
|
|
|
define half @vreduce_fmax_v128f16(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v128f16:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: li a1, 64
|
|
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
|
|
; CHECK-NEXT: vle16.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle16.v v16, (a0)
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <128 x half>, ptr %x
|
|
%red = call half @llvm.vector.reduce.fmax.v128f16(<128 x half> %v)
|
|
ret half %red
|
|
}
|
|
|
|
declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>)
|
|
|
|
define float @vreduce_fmax_v2f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v2f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmax.v2f32(<2 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)
|
|
|
|
define float @vreduce_fmax_v4f32(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
|
|
define float @vreduce_fmax_v4f32_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f32_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
|
|
ret float %red
|
|
}
|
|
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define float @vreduce_fmax_v4f32_nonans_noinfs(ptr %x) {
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; CHECK-LABEL: vreduce_fmax_v4f32_nonans_noinfs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: vfredmax.vs v8, v8, v8
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; CHECK-NEXT: vfmv.f.s fa0, v8
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; CHECK-NEXT: ret
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%v = load <4 x float>, ptr %x
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%red = call nnan ninf float @llvm.vector.reduce.fmax.v4f32(<4 x float> %v)
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ret float %red
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}
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declare float @llvm.vector.reduce.fmax.v128f32(<128 x float>)
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define float @vreduce_fmax_v128f32(ptr %x) {
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; CHECK-LABEL: vreduce_fmax_v128f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a1, 32
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; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
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; CHECK-NEXT: vle32.v v8, (a0)
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; CHECK-NEXT: addi a1, a0, 384
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; CHECK-NEXT: vle32.v v16, (a1)
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; CHECK-NEXT: addi a1, a0, 256
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; CHECK-NEXT: addi a0, a0, 128
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; CHECK-NEXT: vle32.v v24, (a0)
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; CHECK-NEXT: vle32.v v0, (a1)
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; CHECK-NEXT: vfmax.vv v16, v24, v16
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; CHECK-NEXT: vfmax.vv v8, v8, v0
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; CHECK-NEXT: vfmax.vv v8, v8, v16
|
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; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
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; CHECK-NEXT: vfmv.f.s fa0, v8
|
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; CHECK-NEXT: ret
|
|
%v = load <128 x float>, ptr %x
|
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%red = call float @llvm.vector.reduce.fmax.v128f32(<128 x float> %v)
|
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ret float %red
|
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}
|
|
|
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declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)
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|
|
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define double @vreduce_fmax_v2f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v2f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <2 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmax.v2f64(<2 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)
|
|
|
|
define double @vreduce_fmax_v4f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmax_v4f64_nonans(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f64_nonans:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call nnan double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define double @vreduce_fmax_v4f64_nonans_noinfs(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v4f64_nonans_noinfs:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x double>, ptr %x
|
|
%red = call nnan ninf double @llvm.vector.reduce.fmax.v4f64(<4 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
declare double @llvm.vector.reduce.fmax.v32f64(<32 x double>)
|
|
|
|
define double @vreduce_fmax_v32f64(ptr %x) {
|
|
; CHECK-LABEL: vreduce_fmax_v32f64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: addi a0, a0, 128
|
|
; CHECK-NEXT: vle64.v v16, (a0)
|
|
; CHECK-NEXT: vfmax.vv v8, v8, v16
|
|
; CHECK-NEXT: vfredmax.vs v8, v8, v8
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <32 x double>, ptr %x
|
|
%red = call double @llvm.vector.reduce.fmax.v32f64(<32 x double> %v)
|
|
ret double %red
|
|
}
|
|
|
|
define float @vreduce_nsz_fadd_v4f32(ptr %x, float %s) {
|
|
; CHECK-LABEL: vreduce_nsz_fadd_v4f32:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
|
; CHECK-NEXT: vle32.v v8, (a0)
|
|
; CHECK-NEXT: vfmv.s.f v9, fa0
|
|
; CHECK-NEXT: vfredusum.vs v8, v8, v9
|
|
; CHECK-NEXT: vfmv.f.s fa0, v8
|
|
; CHECK-NEXT: ret
|
|
%v = load <4 x float>, ptr %x
|
|
%red = call reassoc nsz float @llvm.vector.reduce.fadd.v4f32(float %s, <4 x float> %v)
|
|
ret float %red
|
|
}
|