127 lines
5.5 KiB
LLVM
127 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
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; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
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%struct = type { i64, i64, ptr, i32, i32, i32, [4 x i32] }
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define void @complex_gep(ptr %p, <vscale x 2 x i64> %vec.ind, <vscale x 2 x i1> %m) {
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; RV32-LABEL: complex_gep:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; RV32-NEXT: vnsrl.wi v10, v8, 0
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; RV32-NEXT: li a1, 48
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; RV32-NEXT: vmul.vx v8, v10, a1
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; RV32-NEXT: addi a0, a0, 28
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; RV32-NEXT: vmv.v.i v9, 0
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; RV32-NEXT: vsoxei32.v v9, (a0), v8, v0.t
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; RV32-NEXT: ret
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;
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; RV64-LABEL: complex_gep:
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; RV64: # %bb.0:
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; RV64-NEXT: li a1, 56
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; RV64-NEXT: vsetvli a2, zero, e64, m2, ta, ma
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; RV64-NEXT: vmul.vx v8, v8, a1
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; RV64-NEXT: addi a0, a0, 32
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; RV64-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; RV64-NEXT: vmv.v.i v10, 0
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; RV64-NEXT: vsoxei64.v v10, (a0), v8, v0.t
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; RV64-NEXT: ret
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%gep = getelementptr inbounds %struct, ptr %p, <vscale x 2 x i64> %vec.ind, i32 5
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call void @llvm.masked.scatter.nxv2i32.nxv2p0(<vscale x 2 x i32> zeroinitializer, <vscale x 2 x ptr> %gep, i32 8, <vscale x 2 x i1> %m)
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ret void
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}
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define void @strided_store_zero_start(i64 %n, ptr %p) {
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; RV32-LABEL: strided_store_zero_start:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; RV32-NEXT: vid.v v8
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; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; RV32-NEXT: vnsrl.wi v8, v8, 0
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; RV32-NEXT: li a0, 48
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; RV32-NEXT: vmul.vx v8, v8, a0
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; RV32-NEXT: addi a0, a2, 32
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; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
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; RV32-NEXT: vmv.v.i v9, 0
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; RV32-NEXT: vsoxei32.v v9, (a0), v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: strided_store_zero_start:
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; RV64: # %bb.0:
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; RV64-NEXT: addi a0, a1, 36
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; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
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; RV64-NEXT: vmv.v.i v8, 0
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; RV64-NEXT: li a1, 56
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; RV64-NEXT: vsse64.v v8, (a0), a1
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; RV64-NEXT: ret
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%step = tail call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
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%gep = getelementptr inbounds %struct, ptr %p, <vscale x 1 x i64> %step, i32 6
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tail call void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x ptr> %gep, i32 8, <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i32 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer))
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ret void
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}
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define void @strided_store_offset_start(i64 %n, ptr %p) {
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; RV32-LABEL: strided_store_offset_start:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
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; RV32-NEXT: vid.v v8
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; RV32-NEXT: vadd.vx v8, v8, a0
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; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; RV32-NEXT: vnsrl.wi v8, v8, 0
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; RV32-NEXT: li a0, 48
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; RV32-NEXT: vmul.vx v8, v8, a0
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; RV32-NEXT: addi a0, a2, 32
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; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
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; RV32-NEXT: vmv.v.i v9, 0
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; RV32-NEXT: vsoxei32.v v9, (a0), v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: strided_store_offset_start:
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; RV64: # %bb.0:
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; RV64-NEXT: li a2, 56
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; RV64-NEXT: mul a0, a0, a2
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; RV64-NEXT: add a0, a1, a0
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; RV64-NEXT: addi a0, a0, 36
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; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
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; RV64-NEXT: vmv.v.i v8, 0
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; RV64-NEXT: vsse64.v v8, (a0), a2
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; RV64-NEXT: ret
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%step = tail call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
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%.splatinsert = insertelement <vscale x 1 x i64> poison, i64 %n, i64 0
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%.splat = shufflevector <vscale x 1 x i64> %.splatinsert, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
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%add = add <vscale x 1 x i64> %step, %.splat
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%gep = getelementptr inbounds %struct, ptr %p, <vscale x 1 x i64> %add, i32 6
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tail call void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x ptr> %gep, i32 8, <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i32 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer))
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ret void
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}
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define void @stride_one_store(i64 %n, ptr %p) {
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; RV32-LABEL: stride_one_store:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; RV32-NEXT: vid.v v8
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; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; RV32-NEXT: vnsrl.wi v8, v8, 0
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; RV32-NEXT: vsll.vi v8, v8, 3
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; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
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; RV32-NEXT: vmv.v.i v9, 0
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; RV32-NEXT: vsoxei32.v v9, (a2), v8
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; RV32-NEXT: ret
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;
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; RV64-LABEL: stride_one_store:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
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; RV64-NEXT: vmv.v.i v8, 0
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; RV64-NEXT: vs1r.v v8, (a1)
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; RV64-NEXT: ret
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%step = tail call <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
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%gep = getelementptr inbounds i64, ptr %p, <vscale x 1 x i64> %step
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tail call void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64> zeroinitializer, <vscale x 1 x ptr> %gep, i32 8, <vscale x 1 x i1> shufflevector (<vscale x 1 x i1> insertelement (<vscale x 1 x i1> poison, i1 true, i32 0), <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer))
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ret void
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}
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declare <vscale x 1 x i64> @llvm.experimental.stepvector.nxv1i64()
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declare void @llvm.masked.scatter.nxv2i32.nxv2p0(<vscale x 2 x i32>, <vscale x 2 x ptr>, i32, <vscale x 2 x i1>)
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declare void @llvm.masked.scatter.nxv1i64.nxv1p0(<vscale x 1 x i64>, <vscale x 1 x ptr>, i32, <vscale x 1 x i1>)
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