136 lines
4 KiB
LLVM
136 lines
4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s
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; Check that each outlining candidate and the outlined function are in agreement
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; with regard to whether BTI insertion is enabled or not.
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; volatile int a, b, c, d, e, f;
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;
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; int x(int p) {
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; int r = (a + b) / (c + d) * e + f;
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; return r + 1;
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; }
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;
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; __attribute__((target("branch-protection=none")))
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; int y(int p) {
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; int r = (a + b) / (c + d) * e + f;
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; return r + 2;
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; }
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;
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; __attribute__((target("branch-protection=bti")))
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; int z(int p) {
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; int r = (a + b) / (c + d) * e + f;
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; return r + 3;
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; }
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@a = hidden global i32 0, align 4
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@b = hidden global i32 0, align 4
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@c = hidden global i32 0, align 4
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@d = hidden global i32 0, align 4
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@e = hidden global i32 0, align 4
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@f = hidden global i32 0, align 4
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define hidden i32 @x(i32 %p) local_unnamed_addr #0 {
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; CHECK-LABEL: x:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: ldr r0, .LCPI0_0
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; CHECK-NEXT: .save {lr}
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; CHECK-NEXT: str lr, [sp, #-8]!
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; CHECK-NEXT: bl OUTLINED_FUNCTION_0
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; CHECK-NEXT: ldr lr, [sp], #8
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; CHECK-NEXT: adds r0, #1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long .L_MergedGlobals
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entry:
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%0 = load volatile i32, ptr @a, align 4
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%1 = load volatile i32, ptr @b, align 4
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%add = add nsw i32 %1, %0
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%2 = load volatile i32, ptr @c, align 4
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%3 = load volatile i32, ptr @d, align 4
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%add1 = add nsw i32 %3, %2
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%div = sdiv i32 %add, %add1
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%4 = load volatile i32, ptr @e, align 4
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%mul = mul nsw i32 %4, %div
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%5 = load volatile i32, ptr @f, align 4
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%add2 = add nsw i32 %mul, %5
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%add3 = add nsw i32 %add2, 1
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ret i32 %add3
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}
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define hidden i32 @y(i32 %p) local_unnamed_addr #1 {
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; CHECK-LABEL: y:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: ldr r0, .LCPI1_0
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; CHECK-NEXT: .save {lr}
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; CHECK-NEXT: str lr, [sp, #-8]!
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; CHECK-NEXT: bl OUTLINED_FUNCTION_0
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; CHECK-NEXT: ldr lr, [sp], #8
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; CHECK-NEXT: adds r0, #2
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI1_0:
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; CHECK-NEXT: .long .L_MergedGlobals
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entry:
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%0 = load volatile i32, ptr @a, align 4
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%1 = load volatile i32, ptr @b, align 4
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%add = add nsw i32 %1, %0
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%2 = load volatile i32, ptr @c, align 4
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%3 = load volatile i32, ptr @d, align 4
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%add1 = add nsw i32 %3, %2
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%div = sdiv i32 %add, %add1
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%4 = load volatile i32, ptr @e, align 4
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%mul = mul nsw i32 %4, %div
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%5 = load volatile i32, ptr @f, align 4
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%add2 = add nsw i32 %mul, %5
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%add3 = add nsw i32 %add2, 2
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ret i32 %add3
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}
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define hidden i32 @z(i32 %p) local_unnamed_addr #2 {
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; CHECK-LABEL: z:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: bti
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; CHECK-NEXT: ldr r0, .LCPI2_0
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; CHECK-NEXT: ldr r1, [r0]
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; CHECK-NEXT: ldr r2, [r0, #4]
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; CHECK-NEXT: add r1, r2
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; CHECK-NEXT: ldr r2, [r0, #8]
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; CHECK-NEXT: ldr r3, [r0, #12]
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; CHECK-NEXT: add r2, r3
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; CHECK-NEXT: sdiv r1, r1, r2
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; CHECK-NEXT: ldr r2, [r0, #16]
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; CHECK-NEXT: ldr r0, [r0, #20]
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; CHECK-NEXT: mla r0, r2, r1, r0
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; CHECK-NEXT: adds r0, #3
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI2_0:
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; CHECK-NEXT: .long .L_MergedGlobals
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entry:
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%0 = load volatile i32, ptr @a, align 4
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%1 = load volatile i32, ptr @b, align 4
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%add = add nsw i32 %1, %0
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%2 = load volatile i32, ptr @c, align 4
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%3 = load volatile i32, ptr @d, align 4
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%add1 = add nsw i32 %3, %2
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%div = sdiv i32 %add, %add1
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%4 = load volatile i32, ptr @e, align 4
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%mul = mul nsw i32 %4, %div
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%5 = load volatile i32, ptr @f, align 4
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%add2 = add nsw i32 %mul, %5
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%add3 = add nsw i32 %add2, 3
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ret i32 %add3
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}
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attributes #0 = { minsize nofree norecurse nounwind optsize }
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attributes #1 = { minsize nofree norecurse nounwind optsize "branch-target-enforcement"="false" }
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attributes #2 = { minsize nofree norecurse nounwind optsize "branch-target-enforcement"="true" }
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!llvm.module.flags = !{!0}
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!0 = !{i32 8, !"branch-target-enforcement", i32 0}
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