50 lines
2.3 KiB
LLVM
50 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+egpr -verify-machineinstrs --show-mc-encoding | FileCheck %s --check-prefix=EGPR
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define void @test_amx(ptr %pointer, ptr %base, i64 %stride) {
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; CHECK-LABEL: test_amx:
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; CHECK: # %bb.0:
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; CHECK-NEXT: ldtilecfg (%rdi)
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; CHECK-NEXT: sttilecfg (%rdi)
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; CHECK-NEXT: tilerelease
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; CHECK-NEXT: tilezero %tmm3
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; CHECK-NEXT: tileloadd (%rsi,%rdx), %tmm3
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; CHECK-NEXT: tileloaddt1 (%rsi,%rdx), %tmm3
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; CHECK-NEXT: tilestored %tmm3, (%rsi,%rdx)
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; CHECK-NEXT: retq
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;
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; EGPR-LABEL: test_amx:
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; EGPR: # %bb.0:
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; EGPR-NEXT: ldtilecfg (%rdi) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x78,0x49,0x07]
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; EGPR-NEXT: sttilecfg (%rdi) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x49,0x07]
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; EGPR-NEXT: tilerelease # encoding: [0xc4,0xe2,0x78,0x49,0xc0]
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; EGPR-NEXT: tilezero %tmm3 # encoding: [0xc4,0xe2,0x7b,0x49,0xd8]
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; EGPR-NEXT: tileloadd (%rsi,%rdx), %tmm3 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7b,0x4b,0x1c,0x16]
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; EGPR-NEXT: tileloaddt1 (%rsi,%rdx), %tmm3 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x4b,0x1c,0x16]
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; EGPR-NEXT: tilestored %tmm3, (%rsi,%rdx) # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x1c,0x16]
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; EGPR-NEXT: retq # encoding: [0xc3]
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call void @llvm.x86.ldtilecfg(ptr %pointer)
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call void @llvm.x86.sttilecfg(ptr %pointer)
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call void @llvm.x86.tilerelease()
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call void @llvm.x86.tilezero(i8 3)
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call void @llvm.x86.tileloadd64(i8 3, ptr %base, i64 %stride)
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call void @llvm.x86.tileloaddt164(i8 3, ptr %base, i64 %stride)
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call void @llvm.x86.tilestored64(i8 3, ptr %base, i64 %stride)
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ret void
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}
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declare void @llvm.x86.tileloadd64(i8 %tile, ptr %base, i64 %stride)
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declare void @llvm.x86.tileloaddt164(i8 %tile, ptr %base, i64 %stride)
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declare void @llvm.x86.tilestored64(i8 %tile, ptr %base, i64 %stride)
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declare void @llvm.x86.ldtilecfg(ptr %pointer)
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declare void @llvm.x86.sttilecfg(ptr %pointer)
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declare void @llvm.x86.tilerelease()
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declare void @llvm.x86.tilezero(i8 %tile)
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