bolt/deps/llvm-18.1.8/llvm/test/CodeGen/X86/GlobalISel/x86-select-trap.mir
2025-02-14 19:21:04 +01:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
declare void @llvm.trap() #0
define i32 @trap() #0 {
tail call void @llvm.trap()
unreachable
}
attributes #0 = { noreturn nounwind }
attributes #1 = { nounwind }
...
---
name: trap
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: trap
; CHECK: TRAP
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
...